initial commit to new repo

This commit is contained in:
Nicole Faerber 2021-02-14 18:03:13 +01:00
parent ccdb239b00
commit adbc36ad71
131 changed files with 52765 additions and 1 deletions

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# Oswald
Smartwatch OS for microctroller based smartwatches, originally developed for MSP430 based MetaWatch
Smartwatch OS for microctroller based smartwatches, originally developed for MSP430 based MetaWatchOSWALD
Open Smart Watch Application Loadable Development
License: LGPL (Gnu Library Public License),
permission granted for static linking,
see individual files for more / different licensing information

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linux-bt/Makefile Normal file
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CFLAGS = -Wall -O2
SRC = l2cap_client.c
PRG = l2cap_client
OBJS = $(SRC:.c=.o)
all: $(PRG)
$(PRG): $(OBJS)
$(CC) -o $(PRG) $(OBJS) -lbluetooth
%.o: %c
$(CC) -c $(CFLAGS) -o $@ $<
clean:
rm -f $(OBJS) $(PRG)

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linux-bt/README.txt Normal file
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l2cap_client
License: GPLv3
This is a small test application to test the Bluetooth connection to
Oswald-MetaWatch. It opens a L2CAP connection to a give Bluetooth address.
After successful connection establishment it output all data received to
stdout and send data received from stdin (keyboard) to the watch. Input via
stdin is not in cbreak mode, i.e. input must be finished with CR before it
is sent to the watch.
Building
Simply type "make". Depend on libbluetooth and its development files.
Running
Start with Bluetooth address of the watch as cmdline argument:
l2cap_client 11:22:33:44:55:66

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linux-bt/l2cap_client.c Normal file
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/*
* (c) 2013 Nicole Faerber, Siegen, Germany
* licensed under GPLv2
*/
#include <stdio.h>
#include <string.h>
#include <unistd.h>
#include <stdlib.h>
#include <sys/select.h>
#include <sys/time.h>
#include <sys/types.h>
#include <sys/socket.h>
#include <fcntl.h>
#include <bluetooth/bluetooth.h>
#include <bluetooth/l2cap.h>
typedef enum {
CMD_NULL = 0,
CMD_INVAL,
CMD_QUIT,
} cmd_t;
// replace "markups" with appropr. chars
char *parse_buffer(char *inbuf, int *cmd)
{
int i,o;
static char outbuf[240];
memset(outbuf,0,240);
*cmd = CMD_NULL;
// if a line starts with a \ then it is an internal command
if (inbuf[0] == '\\') {
switch (inbuf[1]) {
case 'q':
*cmd = CMD_QUIT;
break;
default:
*cmd = CMD_INVAL;
break;
}
return NULL;
}
o=0;
for (i=0; i<strlen(inbuf); i++) {
if (inbuf[i] == '\\') {
i++;
if (inbuf[i] == 'n')
outbuf[o++] = '\n';
} else
outbuf[o++] = inbuf[i];
}
return outbuf;
}
int main(int argc, char **argv)
{
struct sockaddr_l2 addr = { 0 };
int s, status, len, i, cmd;
char buf[255];
char dest[18];
char *out;
fd_set infds;
fd_set efds;
if (argc < 2) {
fprintf(stderr, "usage: %s <bt_addr>\n", argv[0]);
exit(2);
}
strncpy(dest, argv[1], 18);
// allocate a socket
s = socket(AF_BLUETOOTH, SOCK_SEQPACKET, BTPROTO_L2CAP);
// set the connection parameters (who to connect to)
addr.l2_family = AF_BLUETOOTH;
addr.l2_psm = htobs(0x1001);
str2ba( dest, &addr.l2_bdaddr );
// connect to server
status = connect(s, (struct sockaddr *)&addr, sizeof(addr));
// send a message
if ( status != 0 ) {
perror("open socket");
close(s);
return -1;
}
fprintf(stderr, "connected\n");
if (fcntl(0, F_SETFL, O_NONBLOCK) != 0)
perror("stdin nonblock");
if (fcntl(s, F_SETFL, O_NONBLOCK) != 0)
perror("socket nonblock");
while (1) {
FD_ZERO(&infds);
FD_SET(s, &infds);
FD_SET(0, &infds);
FD_ZERO(&efds);
FD_SET(s, &efds);
status = select(s+1, &infds, NULL, &efds, NULL);
// fprintf(stderr, "select = %d\n", status);
if ( status > 0) {
if (FD_ISSET(0, &infds)) {
len = read(0, buf, 240);
if (len > 0) {
// status = write(s, buf, len);
out = parse_buffer(buf, &cmd);
if (cmd != CMD_NULL) {
if (cmd == CMD_QUIT) {
close(s);
exit(0);
}
} else {
len = strlen(out);
status = write(s, out, len);
if (status < 0)
perror("write");
fsync(s);
}
}
} else if (FD_ISSET(s, &infds)) {
len = read(s, buf, 240);
// fprintf(stderr, "read = %d\n", len);
for (i=0; i<len; i++)
fprintf(stderr, "%c", buf[i]);
// fprintf(stderr, "\n");
} else if (FD_ISSET(s, &efds)) {
fprintf(stderr, "e on socket\n");
} else
fprintf(stderr, "hu?");
} else
perror("select");
};
close(s);
return 0;
}

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1 TECHNOLOGY AND SOFTWARE PUBLICLY AVAILABLE
2 SOFTWARE LICENSE
3
4 Copyright (c) 2011, Texas Instruments Incorporated.
5
6 All rights reserved.
7
8 Redistribution.
9
10 Redistribution and use in binary form, without modification, are
11 permitted provided that the following conditions are met:
12
13 * Redistributions must preserve existing copyright notices and reproduce
14 this license (including the above copyright notice and the disclaimer below)
15 in the documentation and/or other materials provided with the distribution.
16
17 * Neither the name of Texas Instruments Incorporated nor the names of
18 its suppliers may be used to endorse or promote products derived
19 from this software without specific prior written permission.
20
21 * No reverse engineering, decompilation, or disassembly of this
22 software is permitted.
23
24 Limited patent license.
25
26 Texas Instruments Incorporated grants a world-wide, royalty-free,
27 non-exclusive license under patents it now or hereafter owns or controls
28 to make, have made, use, import, offer to sell and sell ("Utilize") this
29 software, but solely to the extent that any such patent is necessary
30 to Utilize the software alone. The patent license shall not apply to
31 any combinations which include this software. No hardware per se is
32 licensed hereunder.
33
34 DISCLAIMER.
35
36 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
37 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
38 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
39 A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
40 OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
41 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
42 LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
43 DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
44 THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
45 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
46 OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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1 TECHNOLOGY AND SOFTWARE PUBLICLY AVAILABLE
2 SOFTWARE LICENSE
3
4 Copyright (c) 2011, Texas Instruments Incorporated.
5
6 All rights reserved.
7
8 Redistribution.
9
10 Redistribution and use in binary form, without modification, are
11 permitted provided that the following conditions are met:
12
13 * Redistributions must preserve existing copyright notices and reproduce
14 this license (including the above copyright notice and the disclaimer below)
15 in the documentation and/or other materials provided with the distribution.
16
17 * Neither the name of Texas Instruments Incorporated nor the names of
18 its suppliers may be used to endorse or promote products derived
19 from this software without specific prior written permission.
20
21 * No reverse engineering, decompilation, or disassembly of this
22 software is permitted.
23
24 Limited patent license.
25
26 Texas Instruments Incorporated grants a world-wide, royalty-free,
27 non-exclusive license under patents it now or hereafter owns or controls
28 to make, have made, use, import, offer to sell and sell ("Utilize") this
29 software, but solely to the extent that any such patent is necessary
30 to Utilize the software alone. The patent license shall not apply to
31 any combinations which include this software. No hardware per se is
32 licensed hereunder.
33
34 DISCLAIMER.
35
36 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
37 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
38 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
39 A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
40 OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
41 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
42 LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
43 DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
44 THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
45 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
46 OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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/*******************************************************************************
*
* HAL_FLASH.c
* Flash Library for flash memory controller of MSP430F5xx/6xx family
*
*
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Created: Version 1.0 11/24/2009
* Updated: Version 2.0 01/18/2011
*
******************************************************************************/
#include "msp430.h"
#include "HAL_FLASH.h"
void Flash_SegmentErase(unsigned int *Flash_ptr)
{
FCTL3 = FWKEY; // Clear Lock bit
FCTL1 = FWKEY + ERASE; // Set Erase bit
*Flash_ptr = 0; // Dummy write to erase Flash seg
while (FCTL3 & BUSY); // test busy
FCTL1 = FWKEY; // Clear WRT bit
FCTL3 = FWKEY + LOCK; // Set LOCK bit
}
unsigned char Flash_EraseCheck(unsigned int *Flash_ptr, unsigned int len)
{
unsigned int i;
for (i = 0; i < len; i++) { // was erasing successfull?
if (*(Flash_ptr + i) != 0xFF) {
return FLASH_STATUS_ERROR;
}
}
return FLASH_STATUS_OK;
}
void FlashWrite_8(unsigned char *Data_ptr, unsigned char *Flash_ptr, unsigned int count)
{
FCTL3 = FWKEY; // Clear Lock bit
FCTL1 = FWKEY+WRT; // Enable byte/word write mode
while (count > 0) {
while (FCTL3 & BUSY); // test busy
*Flash_ptr++ = *Data_ptr++; // Write to Flash
count--;
}
FCTL1 = FWKEY; // Clear write bit
FCTL3 = FWKEY + LOCK; // Set LOCK bit
}
void FlashWrite_16(unsigned int *Data_ptr, unsigned int *Flash_ptr, unsigned int count)
{
FCTL3 = FWKEY; // Clear Lock bit
FCTL1 = FWKEY+WRT; // Enable byte/word write mode
while (count > 0) {
while (FCTL3 & BUSY); // test busy
*Flash_ptr++ = *Data_ptr++; // Write to Flash
count--;
}
FCTL1 = FWKEY; // Clear Erase bit
FCTL3 = FWKEY + LOCK; // Set LOCK bit
}
void FlashWrite_32(unsigned long *Data_ptr, unsigned long *Flash_ptr, unsigned int count)
{
FCTL3 = FWKEY; // Clear Lock bit
FCTL1 = FWKEY + BLKWRT; // Enable long-word write
while (count > 0) {
while (FCTL3 & BUSY); // test busy
*Flash_ptr++ = *Data_ptr++; // Write to Flash
count--;
}
FCTL1 = FWKEY; // Clear Erase bit
FCTL3 = FWKEY + LOCK; // Set LOCK bit
}
void FlashMemoryFill_32(unsigned long value, unsigned long *Flash_ptr, unsigned int count)
{
FCTL3 = FWKEY; // Clear Lock bit
FCTL1 = FWKEY + BLKWRT; // Enable long-word write
while (count > 0) {
while (FCTL3 & BUSY); // test busy
*Flash_ptr++ = value; // Write to Flash
count--;
}
FCTL1 = FWKEY; // Clear Erase bit
FCTL3 = FWKEY + LOCK; // Set LOCK bit
}

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/*******************************************************************************
*
* HAL_FLASH.h
* Flash Library for flash memory controller of MSP430F5xx/6xx family
*
*
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Created: Version 1.0 11/24/2009
* Updated: Version 2.0 01/18/2011
*
******************************************************************************/
#ifndef HAL_FLASH_H
#define HAL_FLASH_H
//******************************************************************************
// Defines
//******************************************************************************
#define FLASH_STATUS_OK 0
#define FLASH_STATUS_ERROR 1
/*******************************************************************************
* \brief Erase a single segment of the flash memory
*
* \param *Flash_ptr Pointer into the flash segment to erase
******************************************************************************/
extern void Flash_SegmentErase(unsigned int *Flash_ptr);
/*******************************************************************************
* \brief Erase Check of the flash memory
*
* \param *Flash_ptr Pointer into the flash segment to erase
* \param len give the len in word
******************************************************************************/
extern unsigned char Flash_EraseCheck(unsigned int *Flash_ptr, unsigned int len);
/*******************************************************************************
* \brief Write data into the flash memory (Byte format)
*
* \param *Data_ptr Pointer to the Data to write
* \param *Flash_ptr Pointer into the flash to write data to
* \param count number of data to write
******************************************************************************/
extern void FlashWrite_8(unsigned char *Data_ptr, unsigned char *Flash_ptr, unsigned int count);
/*******************************************************************************
* \brief Write data into the flash memory (Word format)
*
* \param *Data_ptr Pointer to the Data to write
* \param *Flash_ptr Pointer into the flash to write data to
* \param count number of data to write
******************************************************************************/
extern void FlashWrite_16(unsigned int *Data_ptr, unsigned int *Flash_ptr, unsigned int count);
/*******************************************************************************
* \brief Write data into the flash memory (Long format)
*
* \param *Data_ptr Pointer to the Data to write
* \param *Flash_ptr Pointer into the flash to write data to
* \param count number of data to write
******************************************************************************/
extern void FlashWrite_32(unsigned long *Data_ptr, unsigned long *Flash_ptr, unsigned int count);
/*******************************************************************************
* \brief Fill data into the flash memory (Long format)
*
* \param value Pointer to the Data to write
* \param *Flash_ptr pointer into the flash to write data to
* \param count number of data to write (= byte * 4)
******************************************************************************/
extern void FlashMemoryFill_32(unsigned long value, unsigned long *Flash_ptr, unsigned int count);
#endif /* HAL_FLASH_H */

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/* ****************************************************************************
*
* HAL_MACROS.h
* Flash Library for flash memory controller of MSP430F5xx/6xx family
*
*
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Created: Version 1.0 11/24/2009
* Updated: Version 2.0 12/15/2010
*
******************************************************************************/
#ifndef HAL_MACROS_H
#define HAL_MACROS_H
/*
* This macro is for use by other macros to form a fully valid C statement.
*/
#define st(x) do { x } while (__LINE__ == -1)
#endif /* HAL_MACROS_H */

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/*******************************************************************************
*
* HAL_PMAP.c
* Port Mapper Library for PMAP controller of MSP430F5xx/6xx family
*
*
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Created: Version 1.0 11/24/2009
* Updated: Version 2.0 12/15/2010
*
******************************************************************************/
#include "msp430.h"
#include "HAL_PMAP.h"
#include "portmacro.h"
// Check and define PMAP function only if the device has port mapping capability
// Note: This macro is defined in the device-specific header file if this
// feature is available on a given MSP430.
#ifdef __MSP430_HAS_PORT_MAPPING__
void configure_ports(const unsigned char *port_mapping, unsigned char *PxMAPy,
unsigned char num_of_ports, unsigned char port_map_reconfig)
{
uint16_t i;
portENTER_CRITICAL();
// Get write-access to port mapping registers:
PMAPPWD = PMAPPW;
if (port_map_reconfig) {
// Allow reconfiguration during runtime:
PMAPCTL = PMAPRECFG;
}
// Configure Port Mapping:
for (i = 0; i < num_of_ports * 8; i++) {
PxMAPy[i] = port_mapping[i];
}
// Disable write-access to port mapping registers:
PMAPPWD = 0;
portEXIT_CRITICAL();
}
#endif /* __MSP430_HAS_PORT_MAPPING__ */

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/*******************************************************************************
*
* HAL_PMAP.h
* Port Mapper Library for PMAP controller of MSP430F5xx/6xx family
*
*
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Created: Version 1.0 11/24/2009
* Updated: Version 2.0 12/15/2010
*
******************************************************************************/
#ifndef HAL_PMAP_H
#define HAL_PMAP_H
/*******************************************************************************
* \brief Configures the MSP430 Port Mapper
*
* \param *port_mapping Pointer to init Data
* \param PxMAPy Pointer start of first Port Mapper to initialize
* \param num_of_ports Number of Ports to initialize
* \param port_map_reconfig Flag to enable/disable reconfiguration
*
******************************************************************************/
extern void configure_ports(const unsigned char *port_mapping, unsigned char *PxMAPy,
unsigned char num_of_ports, unsigned char port_map_reconfig);
#endif /* HAL_PMAP_H */

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/*******************************************************************************
*
* HAL_PMM.c
* Power Management Module Library for MSP430F5xx/6xx family
*
*
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Created: Version 1.0 11/24/2009
* Updated: Version 2.0 12/15/2010
* Modified SetVcoreUp() and SetVcoreDown() functions
*
******************************************************************************/
#include "msp430.h"
#include "HAL_PMM.h"
#define _HAL_PMM_DISABLE_SVML_
#define _HAL_PMM_DISABLE_SVSL_
#define _HAL_PMM_DISABLE_FULL_PERFORMANCE_
#ifdef _HAL_PMM_DISABLE_SVML_
#define _HAL_PMM_SVMLE SVMLE
#else
#define _HAL_PMM_SVMLE 0
#endif
#ifdef _HAL_PMM_DISABLE_SVSL_
#define _HAL_PMM_SVSLE SVSLE
#else
#define _HAL_PMM_SVSLE 0
#endif
#ifdef _HAL_PMM_DISABLE_FULL_PERFORMANCE_
#define _HAL_PMM_SVSFP SVSLFP
#define _HAL_PMM_SVMFP SVMLFP
#else
#define _HAL_PMM_SVSFP 0
#define _HAL_PMM_SVMFP 0
#endif
/*******************************************************************************
* \brief Increase Vcore by one level
*
* \param level Level to which Vcore needs to be increased
* \return status Success/failure
******************************************************************************/
static unsigned int SetVCoreUp(unsigned char level)
{
unsigned int PMMRIE_backup, SVSMHCTL_backup, SVSMLCTL_backup;
// The code flow for increasing the Vcore has been altered to work around
// the erratum FLASH37.
// Please refer to the Errata sheet to know if a specific device is affected
// DO NOT ALTER THIS FUNCTION
// Open PMM registers for write access
PMMCTL0_H = 0xA5;
// Disable dedicated Interrupts
// Backup all registers
PMMRIE_backup = PMMRIE;
PMMRIE &= ~(SVMHVLRPE | SVSHPE | SVMLVLRPE | SVSLPE | SVMHVLRIE |
SVMHIE | SVSMHDLYIE | SVMLVLRIE | SVMLIE | SVSMLDLYIE );
SVSMHCTL_backup = SVSMHCTL;
SVSMLCTL_backup = SVSMLCTL;
// Clear flags
PMMIFG = 0;
// Set SVM highside to new level and check if a VCore increase is possible
SVSMHCTL = SVMHE | SVSHE | (SVSMHRRL0 * level);
// Wait until SVM highside is settled
while ((PMMIFG & SVSMHDLYIFG) == 0);
// Clear flag
PMMIFG &= ~SVSMHDLYIFG;
// Check if a VCore increase is possible
if ((PMMIFG & SVMHIFG) == SVMHIFG) { // -> Vcc is too low for a Vcore increase
// recover the previous settings
PMMIFG &= ~SVSMHDLYIFG;
SVSMHCTL = SVSMHCTL_backup;
// Wait until SVM highside is settled
while ((PMMIFG & SVSMHDLYIFG) == 0);
// Clear all Flags
PMMIFG &= ~(SVMHVLRIFG | SVMHIFG | SVSMHDLYIFG | SVMLVLRIFG | SVMLIFG | SVSMLDLYIFG);
PMMRIE = PMMRIE_backup; // Restore PMM interrupt enable register
PMMCTL0_H = 0x00; // Lock PMM registers for write access
return PMM_STATUS_ERROR; // return: voltage not set
}
// Set also SVS highside to new level
// Vcc is high enough for a Vcore increase
SVSMHCTL |= (SVSHRVL0 * level);
// Wait until SVM highside is settled
while ((PMMIFG & SVSMHDLYIFG) == 0);
// Clear flag
PMMIFG &= ~SVSMHDLYIFG;
// Set VCore to new level
PMMCTL0_L = PMMCOREV0 * level;
// Set SVM, SVS low side to new level
SVSMLCTL = SVMLE | (SVSMLRRL0 * level) | SVSLE | (SVSLRVL0 * level);
// Wait until SVM, SVS low side is settled
while ((PMMIFG & SVSMLDLYIFG) == 0);
// Clear flag
PMMIFG &= ~SVSMLDLYIFG;
// SVS, SVM core and high side are now set to protect for the new core level
// Restore Low side settings
// Clear all other bits _except_ level settings
SVSMLCTL &= (SVSLRVL0+SVSLRVL1+SVSMLRRL0+SVSMLRRL1+SVSMLRRL2);
// Clear level settings in the backup register,keep all other bits
SVSMLCTL_backup &= ~(SVSLRVL0+SVSLRVL1+SVSMLRRL0+SVSMLRRL1+SVSMLRRL2);
// Restore low-side SVS monitor settings
SVSMLCTL |= SVSMLCTL_backup;
// Restore High side settings
// Clear all other bits except level settings
SVSMHCTL &= (SVSHRVL0+SVSHRVL1+SVSMHRRL0+SVSMHRRL1+SVSMHRRL2);
// Clear level settings in the backup register,keep all other bits
SVSMHCTL_backup &= ~(SVSHRVL0+SVSHRVL1+SVSMHRRL0+SVSMHRRL1+SVSMHRRL2);
// Restore backup
SVSMHCTL |= SVSMHCTL_backup;
// Wait until high side, low side settled
while (((PMMIFG & SVSMLDLYIFG) == 0) && ((PMMIFG & SVSMHDLYIFG) == 0));
// Clear all Flags
PMMIFG &= ~(SVMHVLRIFG | SVMHIFG | SVSMHDLYIFG | SVMLVLRIFG | SVMLIFG | SVSMLDLYIFG);
PMMRIE = PMMRIE_backup; // Restore PMM interrupt enable register
PMMCTL0_H = 0x00; // Lock PMM registers for write access
return PMM_STATUS_OK;
}
/*******************************************************************************
* \brief Decrease Vcore by one level
*
* \param level Level to which Vcore needs to be decreased
* \return status Success/failure
******************************************************************************/
static unsigned int SetVCoreDown(unsigned char level)
{
unsigned int PMMRIE_backup, SVSMHCTL_backup, SVSMLCTL_backup;
// The code flow for decreasing the Vcore has been altered to work around
// the erratum FLASH37.
// Please refer to the Errata sheet to know if a specific device is affected
// DO NOT ALTER THIS FUNCTION
// Open PMM registers for write access
PMMCTL0_H = 0xA5;
// Disable dedicated Interrupts
// Backup all registers
PMMRIE_backup = PMMRIE;
PMMRIE &= ~(SVMHVLRPE | SVSHPE | SVMLVLRPE | SVSLPE | SVMHVLRIE |
SVMHIE | SVSMHDLYIE | SVMLVLRIE | SVMLIE | SVSMLDLYIE );
SVSMHCTL_backup = SVSMHCTL;
SVSMLCTL_backup = SVSMLCTL;
// Clear flags
PMMIFG &= ~(SVMHIFG | SVSMHDLYIFG | SVMLIFG | SVSMLDLYIFG);
// Set SVM, SVS high & low side to new settings in normal mode
SVSMHCTL = SVMHE | (SVSMHRRL0 * level) | SVSHE | (SVSHRVL0 * level);
SVSMLCTL = SVMLE | (SVSMLRRL0 * level) | SVSLE | (SVSLRVL0 * level);
// Wait until SVM high side and SVM low side is settled
while ((PMMIFG & SVSMHDLYIFG) == 0 || (PMMIFG & SVSMLDLYIFG) == 0);
// Clear flags
PMMIFG &= ~(SVSMHDLYIFG + SVSMLDLYIFG);
// SVS, SVM core and high side are now set to protect for the new core level
// Set VCore to new level
PMMCTL0_L = PMMCOREV0 * level;
// Restore Low side settings
// Clear all other bits _except_ level settings
SVSMLCTL &= (SVSLRVL0+SVSLRVL1+SVSMLRRL0+SVSMLRRL1+SVSMLRRL2);
// Clear level settings in the backup register,keep all other bits
SVSMLCTL_backup &= ~(SVSLRVL0+SVSLRVL1+SVSMLRRL0+SVSMLRRL1+SVSMLRRL2);
// Restore low-side SVS monitor settings
SVSMLCTL |= SVSMLCTL_backup;
// Restore High side settings
// Clear all other bits except level settings
SVSMHCTL &= (SVSHRVL0+SVSHRVL1+SVSMHRRL0+SVSMHRRL1+SVSMHRRL2);
// Clear level settings in the backup register, keep all other bits
SVSMHCTL_backup &= ~(SVSHRVL0+SVSHRVL1+SVSMHRRL0+SVSMHRRL1+SVSMHRRL2);
// Restore backup
SVSMHCTL |= SVSMHCTL_backup;
// Wait until high side, low side settled
while (((PMMIFG & SVSMLDLYIFG) == 0) && ((PMMIFG & SVSMHDLYIFG) == 0));
// Clear all Flags
PMMIFG &= ~(SVMHVLRIFG | SVMHIFG | SVSMHDLYIFG | SVMLVLRIFG | SVMLIFG | SVSMLDLYIFG);
PMMRIE = PMMRIE_backup; // Restore PMM interrupt enable register
PMMCTL0_H = 0x00; // Lock PMM registers for write access
return PMM_STATUS_OK; // Return: OK
}
unsigned int SetVCore(unsigned char level)
{
unsigned int actlevel;
unsigned int status;
status = 0;
level &= PMMCOREV_3; // Set Mask for Max. level
actlevel = (PMMCTL0 & PMMCOREV_3); // Get actual VCore
// step by step increase or decrease
while (((level != actlevel) && (status == 0)) || (level < actlevel)) {
if (level > actlevel) {
status = SetVCoreUp(++actlevel);
}
else {
status = SetVCoreDown(--actlevel);
}
}
return status;
}

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HAL_PMM.o: F5xx_F6xx_Core_Lib/HAL_PMM.c \
/opt/msp430/lib/gcc/msp430/4.7.0/../../../../msp430/include/msp430.h \
/opt/msp430/lib/gcc/msp430/4.7.0/../../../../msp430/include/msp430f5438a.h \
/opt/msp430/lib/gcc/msp430/4.7.0/../../../../msp430/include/iomacros.h \
/opt/msp430/lib/gcc/msp430/4.7.0/../../../../msp430/include/in430.h \
/opt/msp430/lib/gcc/msp430/4.7.0/../../../../msp430/include/intrinsics.h \
F5xx_F6xx_Core_Lib/HAL_PMM.h F5xx_F6xx_Core_Lib/HAL_MACROS.h

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/*******************************************************************************
*
* HAL_PMM.h
* Power Management Module Library for MSP430F5xx/6xx family
*
*
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Created: Version 1.0 11/24/2009
* Updated: Version 2.0 12/15/2010
*
******************************************************************************/
#ifndef HAL_PMM_H
#define HAL_PMM_H
#include "HAL_MACROS.h"
/*******************************************************************************
* Macros
******************************************************************************/
#define ENABLE_SVSL() st(PMMCTL0_H = 0xA5; SVSMLCTL |= SVSLE; PMMCTL0_H = 0x00;)
#define DISABLE_SVSL() st(PMMCTL0_H = 0xA5; SVSMLCTL &= ~SVSLE; PMMCTL0_H = 0x00;)
#define ENABLE_SVML() st(PMMCTL0_H = 0xA5; SVSMLCTL |= SVMLE; PMMCTL0_H = 0x00;)
#define DISABLE_SVML() st(PMMCTL0_H = 0xA5; SVSMLCTL &= ~SVMLE; PMMCTL0_H = 0x00;)
#define ENABLE_SVSH() st(PMMCTL0_H = 0xA5; SVSMHCTL |= SVSHE; PMMCTL0_H = 0x00;)
#define DISABLE_SVSH() st(PMMCTL0_H = 0xA5; SVSMHCTL &= ~SVSHE; PMMCTL0_H = 0x00;)
#define ENABLE_SVMH() st(PMMCTL0_H = 0xA5; SVSMHCTL |= SVMHE; PMMCTL0_H = 0x00;)
#define DISABLE_SVMH() st(PMMCTL0_H = 0xA5; SVSMHCTL &= ~SVMHE; PMMCTL0_H = 0x00;)
#define ENABLE_SVSL_SVML() st(PMMCTL0_H = 0xA5; SVSMLCTL |= (SVSLE + SVMLE); PMMCTL0_H = 0x00;)
#define DISABLE_SVSL_SVML() st(PMMCTL0_H = 0xA5; SVSMLCTL &= ~(SVSLE + SVMLE); PMMCTL0_H = 0x00;)
#define ENABLE_SVSH_SVMH() st(PMMCTL0_H = 0xA5; SVSMHCTL |= (SVSHE + SVMHE); PMMCTL0_H = 0x00;)
#define DISABLE_SVSH_SVMH() st(PMMCTL0_H = 0xA5; SVSMHCTL &= ~(SVSHE + SVMHE); PMMCTL0_H = 0x00;)
#define ENABLE_SVSL_RESET() st(PMMCTL0_H = 0xA5; PMMRIE |= SVSLPE; PMMCTL0_H = 0x00;)
#define DISABLE_SVSL_RESET() st(PMMCTL0_H = 0xA5; PMMRIE &= ~SVSLPE; PMMCTL0_H = 0x00;)
#define ENABLE_SVML_INTERRUPT() st(PMMCTL0_H = 0xA5; PMMRIE |= SVMLIE; PMMCTL0_H = 0x00;)
#define DISABLE_SVML_INTERRUPT() st(PMMCTL0_H = 0xA5; PMMRIE &= ~SVMLIE; PMMCTL0_H = 0x00;)
#define ENABLE_SVSH_RESET() st(PMMCTL0_H = 0xA5; PMMRIE |= SVSHPE; PMMCTL0_H = 0x00;)
#define DISABLE_SVSH_RESET() st(PMMCTL0_H = 0xA5; PMMRIE &= ~SVSHPE; PMMCTL0_H = 0x00;)
#define ENABLE_SVMH_INTERRUPT() st(PMMCTL0_H = 0xA5; PMMRIE |= SVMHIE; PMMCTL0_H = 0x00;)
#define DISABLE_SVMH_INTERRUPT() st(PMMCTL0_H = 0xA5; PMMRIE &= ~SVMHIE; PMMCTL0_H = 0x00;)
#define CLEAR_PMM_IFGS() st(PMMCTL0_H = 0xA5; PMMIFG = 0; PMMCTL0_H = 0x00;)
// These settings use SVSH/LACE = 0
#define SVSL_ENABLED_IN_LPM_FAST_WAKE() st(PMMCTL0_H = 0xA5; SVSMLCTL |= (SVSLFP+SVSLMD); SVSMLCTL &= ~SVSMLACE; PMMCTL0_H = 0x00;)
#define SVSL_ENABLED_IN_LPM_SLOW_WAKE() st(PMMCTL0_H = 0xA5; SVSMLCTL |= SVSLMD; SVSMLCTL &= ~(SVSLFP+SVSMLACE); PMMCTL0_H = 0x00;)
#define SVSL_DISABLED_IN_LPM_FAST_WAKE() st(PMMCTL0_H = 0xA5; SVSMLCTL |= SVSLFP; SVSMLCTL &= ~(SVSLMD+SVSMLACE); PMMCTL0_H = 0x00;)
#define SVSL_DISABLED_IN_LPM_SLOW_WAKE() st(PMMCTL0_H = 0xA5; SVSMLCTL &= ~(SVSLFP+SVSMLACE+SVSLMD); PMMCTL0_H = 0x00;)
#define SVSH_ENABLED_IN_LPM_NORM_PERF() st(PMMCTL0_H = 0xA5; SVSMHCTL |= SVSHMD; SVSMHCTL &= ~(SVSMHACE+SVSHFP); PMMCTL0_H = 0x00;)
#define SVSH_ENABLED_IN_LPM_FULL_PERF() st(PMMCTL0_H = 0xA5; SVSMHCTL |= (SVSHMD+SVSHFP); SVSMHCTL &= ~SVSMHACE; PMMCTL0_H = 0x00;)
#define SVSH_DISABLED_IN_LPM_NORM_PERF() st(PMMCTL0_H = 0xA5; SVSMHCTL &= ~(SVSMHACE+SVSHFP+SVSHMD);PMMCTL0_H = 0x00;)
#define SVSH_DISABLED_IN_LPM_FULL_PERF() st(PMMCTL0_H = 0xA5; SVSMHCTL |= SVSHFP; SVSMHCTL &= ~(SVSMHACE+SVSHMD); PMMCTL0_H = 0x00;)
// These setting use SVSH/LACE = 1
#define SVSL_OPTIMIZED_IN_LPM_FAST_WAKE() st(PMMCTL0_H = 0xA5; SVSMLCTL |= (SVSLFP+SVSLMD+SVSMLACE); PMMCTL0_H = 0x00;)
#define SVSH_OPTIMIZED_IN_LPM_FULL_PERF() st(PMMCTL0_H = 0xA5; SVSMHCTL |= (SVSHMD+SVSHFP+SVSMHACE); PMMCTL0_H = 0x00;)
/*******************************************************************************
* Defines
******************************************************************************/
#define PMM_STATUS_OK 0
#define PMM_STATUS_ERROR 1
/*******************************************************************************
* \brief Set Vcore to expected level
*
* \param level Level to which Vcore needs to be increased/decreased
* \return status Success/failure
******************************************************************************/
extern unsigned int SetVCore(unsigned char level);
#endif /* HAL_PMM_H */

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/*******************************************************************************
*
* HAL_TLV.c
* Provides Functions to Read the TLV Data Section of the MSP430 Devices
*
*
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Updated: Version 2.0 01/17/2011
*
******************************************************************************/
#include "msp430.h"
#include "HAL_TLV.h"
void Get_TLV_Info(unsigned char tag, unsigned char instance, unsigned char *length, unsigned int **data_address)
{
char *TLV_address = (char *)TLV_START; // TLV Structure Start Address
while((TLV_address < (char *)TLV_END)
&& ((*TLV_address != tag) || instance) // check for tag and instance
&& (*TLV_address != TLV_TAGEND)) // do range check first
{
if (*TLV_address == tag) instance--; // repeat till requested instance is reached
TLV_address += *(TLV_address + 1) + 2; // add (Current TAG address + LENGTH) + 2
}
if (*TLV_address == tag) // Check if Tag match happened..
{
*length = *(TLV_address + 1); // Return length = Address + 1
*data_address = (unsigned int *)(TLV_address + 2); // Return address of first data/value info = Address + 2
}
else // If there was no tag match and the end of TLV structure was reached..
{
*length = 0; // Return 0 for TAG not found
*data_address = 0; // Return 0 for TAG not found
}
}
unsigned int Get_Device_Type(void)
{
unsigned int *pDeviceType = (unsigned int *)DEVICE_ID_0;
return pDeviceType[0]; // Return Value from TLV Table
}
unsigned int Get_TLV_Memory(unsigned char instance)
{
unsigned char *pPDTAG;
unsigned char bPDTAG_bytes;
unsigned int count;
instance *= 2; // set tag for word access comparison
// TLV access Function Call
Get_TLV_Info(TLV_PDTAG, 0, &bPDTAG_bytes, (unsigned int **)&pPDTAG); // Get Peripheral data pointer
for (count = 0;count <= instance; count += 2)
{
if (pPDTAG[count] == 0) return 0; // Return 0 if end reached
if (count == instance) return (pPDTAG[count] | pPDTAG[count+1]<<8);
}
return 0; // Return 0: not found
}
unsigned int Get_TLV_Peripheral(unsigned char tag, unsigned char instance)
{
unsigned char *pPDTAG;
unsigned char bPDTAG_bytes;
unsigned int count = 0;
unsigned int pcount = 0;
Get_TLV_Info(TLV_PDTAG, 0, &bPDTAG_bytes, (unsigned int **)&pPDTAG); // Get Peripheral data pointer
// read memory configuration from TLV to get offset for Peripherals
while (Get_TLV_Memory(count)) {
count++;
}
pcount = pPDTAG[count * 2 + 1]; // get number of Peripheral entries
count++; // inc count to first Periperal
pPDTAG += count*2; // adjust point to first address of Peripheral
count = 0; // set counter back to 0
pcount *= 2; // align pcount for work comparision
// TLV access Function Call
for (count = 0; count <= pcount; count += 2) {
if (pPDTAG[count+1] == tag) { // test if required Peripheral is found
if (instance > 0) { // test if required instance is found
instance--;
}
else {
return (pPDTAG[count] | pPDTAG[count + 1] << 8); // Return found data
}
}
}
return 0; // Return 0: not found
}
unsigned char Get_TLV_Interrupt(unsigned char tag)
{
unsigned char *pPDTAG;
unsigned char bPDTAG_bytes;
unsigned int count = 0;
unsigned int pcount = 0;
Get_TLV_Info(TLV_PDTAG, 0, &bPDTAG_bytes, (unsigned int **)&pPDTAG); // Get Peripheral data pointer
// read memory configuration from TLV to get offset for Peripherals
while (Get_TLV_Memory(count))
{
count++;
}
pcount = pPDTAG[count * 2 + 1];
count++; // inc count to first Periperal
pPDTAG += (pcount + count) * 2; // adjust point to first address of Peripheral
count = 0; // set counter back to 0
// TLV access Function Call
for (count = 0; count <= tag; count += 2)
{
if (pPDTAG[count] == 0) return 0; // Return 0: not found/end of table
if (count == tag) return (pPDTAG[count]); // Return found data
}
return 0; // Return 0: not found
}

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/*******************************************************************************
*
* HAL_TLV.c
* Provides Functions to Read the TLV Data Section of the MSP430 Devices
*
*
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Updated: Version 2.0 01/17/2011
*
******************************************************************************/
#ifndef HAL_TLV_H
#define HAL_TLV_H
/*******************************************************************************
* Device Descriptors - Fixed Memory Locations
******************************************************************************/
#define DEVICE_ID_0 (0x1A04)
#define DEVICE_ID_1 (0x1A05)
/*******************************************************************************
* Data Types
******************************************************************************/
struct s_TLV_Die_Record {
unsigned char die_record[10];
};
struct s_TLV_ADC_Cal_Data {
unsigned int adc_gain_factor;
unsigned int adc_offset;
unsigned int adc_ref15_30_temp;
unsigned int adc_ref15_85_temp;
unsigned int adc_ref20_30_temp;
unsigned int adc_ref20_85_temp;
unsigned int adc_ref25_30_temp;
unsigned int adc_ref25_85_temp;
};
struct s_TLV_Timer_D_Cal_Data {
unsigned int TDH0CTL1_64;
unsigned int TDH0CTL1_128;
unsigned int TDH0CTL1_200;
unsigned int TDH0CTL1_256;
};
struct s_TLV_REF_Cal_Data {
unsigned int ref_ref15;
unsigned int ref_ref20;
unsigned int adc_ref25;
};
/*******************************************************************************
* Tag Defines
******************************************************************************/
#define TLV_LDTAG (0x01) /* Legacy descriptor (1xx, 2xx,
4xx families) */
#define TLV_PDTAG (0x02) /* Peripheral discovery descriptor */
#define TLV_Reserved3 (0x03) /* Future usage */
#define TLV_Reserved4 (0x04) /* Future usage */
#define TLV_BLANK (0x05) /* Blank descriptor */
#define TLV_Reserved6 (0x06) /* Future usage */
#define TLV_Reserved7 (0x07) /* Serial Number */
#define TLV_DIERECORD (0x08) /* Die Record */
#define TLV_ADCCAL (0x11) /* ADC12 calibration */
#define TLV_ADC12CAL (0x11) /* ADC12 calibration */
#define TLV_ADC10CAL (0x13) /* ADC10 calibration */
#define TLV_REFCAL (0x12) /* REF calibration */
#define TLV_TIMER_D_CAL (0x15) /* Timer_Dx calibration */
#define TLV_TAGEXT (0xFE) /* Tag extender */
#define TLV_TAGEND (0xFF) /* Tag End of Table */
/*******************************************************************************
* Peripheral Defines
******************************************************************************/
#define TLV_PID_NO_MODULE (0x00) /* No Module */
#define TLV_PID_PORTMAPPING (0x10) /* Port Mapping */
#define TLV_PID_MSP430CPUXV2 (0x23) /* MSP430CPUXV2 */
#define TLV_PID_JTAG (0x09) /* JTAG */
#define TLV_PID_SBW (0x0F) /* SBW */
#define TLV_PID_EEM_XS (0x02) /* EEM X-Small */
#define TLV_PID_EEM_S (0x03) /* EEM Small */
#define TLV_PID_EEM_M (0x04) /* EEM Medium */
#define TLV_PID_EEM_L (0x05) /* EEM Large */
#define TLV_PID_PMM (0x30) /* PMM */
#define TLV_PID_PMM_FR (0x32) /* PMM FRAM */
#define TLV_PID_FCTL (0x39) /* Flash */
#define TLV_PID_CRC16 (0x3C) /* CRC16 */
#define TLV_PID_CRC16_RB (0x3D) /* CRC16 Reverse */
#define TLV_PID_WDT_A (0x40) /* WDT_A */
#define TLV_PID_SFR (0x41) /* SFR */
#define TLV_PID_SYS (0x42) /* SYS */
#define TLV_PID_RAMCTL (0x44) /* RAMCTL */
#define TLV_PID_DMA_1 (0x46) /* DMA 1 */
#define TLV_PID_DMA_3 (0x47) /* DMA 3 */
#define TLV_PID_UCS (0x48) /* UCS */
#define TLV_PID_DMA_6 (0x4A) /* DMA 6 */
#define TLV_PID_DMA_2 (0x4B) /* DMA 2 */
#define TLV_PID_PORT1_2 (0x51) /* Port 1 + 2 / A */
#define TLV_PID_PORT3_4 (0x52) /* Port 3 + 4 / B */
#define TLV_PID_PORT5_6 (0x53) /* Port 5 + 6 / C */
#define TLV_PID_PORT7_8 (0x54) /* Port 7 + 8 / D */
#define TLV_PID_PORT9_10 (0x55) /* Port 9 + 10 / E */
#define TLV_PID_PORT11_12 (0x56) /* Port 11 + 12 / F */
#define TLV_PID_PORTU (0x5E) /* Port U */
#define TLV_PID_PORTJ (0x5F) /* Port J */
#define TLV_PID_TA2 (0x60) /* Timer A2 */
#define TLV_PID_TA3 (0x61) /* Timer A1 */
#define TLV_PID_TA5 (0x62) /* Timer A5 */
#define TLV_PID_TA7 (0x63) /* Timer A7 */
#define TLV_PID_TB3 (0x65) /* Timer B3 */
#define TLV_PID_TB5 (0x66) /* Timer B5 */
#define TLV_PID_TB7 (0x67) /* Timer B7 */
#define TLV_PID_RTC (0x68) /* RTC */
#define TLV_PID_BT_RTC (0x69) /* BT + RTC */
#define TLV_PID_BBS (0x6A) /* Battery Backup Switch */
#define TLV_PID_RTC_B (0x6B) /* RTC_B */
#define TLV_PID_TD2 (0x6C) /* Timer D2 */
#define TLV_PID_TD3 (0x6D) /* Timer D1 */
#define TLV_PID_TD5 (0x6E) /* Timer D5 */
#define TLV_PID_TD7 (0x6F) /* Timer D7 */
#define TLV_PID_TEC (0x70) /* Imer Event Control */
#define TLV_PID_RTC_C (0x71) /* RTC_C */
#define TLV_PID_AES (0x80) /* AES */
#define TLV_PID_MPY16 (0x84) /* MPY16 */
#define TLV_PID_MPY32 (0x85) /* MPY32 */
#define TLV_PID_MPU (0x86) /* MPU */
#define TLV_PID_USCI_AB (0x90) /* USCI_AB */
#define TLV_PID_USCI_A (0x91) /* USCI_A */
#define TLV_PID_USCI_B (0x92) /* USCI_B */
#define TLV_PID_EUSCI_A (0x94) /* eUSCI_A */
#define TLV_PID_EUSCI_B (0x95) /* eUSCI_B */
#define TLV_PID_REF (0xA0) /* Shared Reference */
#define TLV_PID_COMP_B (0xA8) /* COMP_B */
#define TLV_PID_COMP_D (0xA9) /* COMP_D */
#define TLV_PID_USB (0x98) /* USB */
#define TLV_PID_LCD_B (0xB1) /* LCD_B */
#define TLV_PID_LCD_C (0xB2) /* LCD_C */
#define TLV_PID_DAC12_A (0xC0) /* DAC12_A */
#define TLV_PID_SD16_B_1 (0xC8) /* SD16_B 1 Channel */
#define TLV_PID_SD16_B_2 (0xC9) /* SD16_B 2 Channel */
#define TLV_PID_SD16_B_3 (0xCA) /* SD16_B 3 Channel */
#define TLV_PID_SD16_B_4 (0xCB) /* SD16_B 4 Channel */
#define TLV_PID_SD16_B_5 (0xCC) /* SD16_B 5 Channel */
#define TLV_PID_SD16_B_6 (0xCD) /* SD16_B 6 Channel */
#define TLV_PID_SD16_B_7 (0xCE) /* SD16_B 7 Channel */
#define TLV_PID_SD16_B_8 (0xCF) /* SD16_B 8 Channel */
#define TLV_PID_ADC12_A (0xD1) /* ADC12_A */
#define TLV_PID_ADC10_A (0xD3) /* ADC10_A */
#define TLV_PID_ADC10_B (0xD4) /* ADC10_B */
#define TLV_PID_SD16_A (0xD8) /* SD16_A */
#define TLV_PID_TI_BSL (0xFC) /* BSL */
/*******************************************************************************
* \brief Get Information out of the TLV Table
*
* \param tag Tag of the TLV entry
* \param instance Instance of the Tag of the TLV entry
* \param *length return: Length of the information if found
* \param **data_address return: start pointer of Data
******************************************************************************/
void Get_TLV_Info(unsigned char tag, unsigned char instance, unsigned char *length,
unsigned int **data_address);
/*******************************************************************************
* \brief Get Device Type out of the TLV Table
*
* \return Device dependent value
******************************************************************************/
unsigned int Get_Device_Type(void);
/*******************************************************************************
* \brief Get Memory Info out of the TLV Table
*
* \param instance Index of the Instance [0..]
* \return Memory Data found
******************************************************************************/
unsigned int Get_TLV_Memory(unsigned char instance);
/*******************************************************************************
* \brief Get Peripheral Info out of the TLV Table
*
* \param tag Tag of the TLV entry
* \param instance Index of the Instance [0..]
* \return Peripheral Data found
******************************************************************************/
unsigned int Get_TLV_Peripheral(unsigned char tag, unsigned char instance);
/*******************************************************************************
* \brief Get Interrupt Info out of the TLV Table
*
* \param tag Tag of the TLV entry
* \return Interrupt Data found
******************************************************************************/
unsigned char Get_TLV_Interrupt(unsigned char tag);
#endif /* HAL_TLV_H */

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/*******************************************************************************
*
* HAL_UCS.c
* Provides Functions to Initialize the UCS/FLL and clock sources
*
*
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Created: Version 1.0 11/24/2009
* Updated: Version 2.0 12/15/2010
* Added Functions: XT2_Stop() and XT1_Stop()
* Modified all functions to preserve drive settings
*
******************************************************************************/
#include "msp430.h"
#include "HAL_UCS.h"
// #include "hal_calibration.h"
/*******************************************************************************
* Check and define required Defines
******************************************************************************/
#ifndef XT1LFOFFG // Defines if not available in header file
#define XT1LFOFFG 0
#endif
#ifndef XT1HFOFFG // Defines if not available in header file
#define XT1HFOFFG 0
#endif
#ifndef XT2OFFG // Defines if not available in header file
#define XT2OFFG 0
#endif
#ifndef XTS // Defines if not available in header file
#define XTS 0
#endif
#ifndef XT2DRIVE_3 // Defines if not available in header file
#define XT2DRIVE_3 0
#endif
/*******************************************************************************
* \brief Initializes FLL of the UCS
*
* \param fsystem Required system frequency (MCLK) in kHz
* \param ratio Ratio between fsystem and FLLREFCLK
******************************************************************************/
static void Init_FLL(unsigned int fsystem, unsigned int ratio);
#if 0
void LFXT_Start(unsigned int xtdrive)
{
// If the drive setting is not already set to maximum
// Set it to max for LFXT startup
if ((UCSCTL6 & XT1DRIVE_3)!= XT1DRIVE_3) {
UCSCTL6_L |= XT1DRIVE1_L + XT1DRIVE0_L; // Highest drive setting for XT1startup
}
while (SFRIFG1 & OFIFG) { // Check OFIFG fault flag
UCSCTL7 &= ~(DCOFFG+XT1LFOFFG+XT1HFOFFG+XT2OFFG); // Clear OSC flaut Flags fault flags
SFRIFG1 &= ~OFIFG; // Clear OFIFG fault flag
}
UCSCTL6 = (UCSCTL6 & ~(XT1DRIVE_3)) | (xtdrive); // set requested Drive mode
}
#endif
unsigned int LFXT_Start_Timeout(unsigned int xtdrive, unsigned int timeout)
{
// add in capacitor setting
//SetOscillatorCapacitorValues();
// If the drive setting is not already set to maximum
// Set it to max for LFXT startup
if ((UCSCTL6 & XT1DRIVE_3)!= XT1DRIVE_3) {
UCSCTL6_L |= XT1DRIVE1_L+XT1DRIVE0_L; // Highest drive setting for XT1startup
}
while ((SFRIFG1 & OFIFG) && timeout--){ // Check OFIFG fault flag
UCSCTL7 &= ~(DCOFFG+XT1LFOFFG+XT1HFOFFG+XT2OFFG); // Clear OSC flaut Flags fault flags
SFRIFG1 &= ~OFIFG; // Clear OFIFG fault flag
}
UCSCTL6 = (UCSCTL6 & ~(XT1DRIVE_3)) |(xtdrive); // set Drive mode
// add in capacitor setting
//SetOscillatorCapacitorValues();
if (timeout)
return (UCS_STATUS_OK);
else
return (UCS_STATUS_ERROR);
}
#if 0
void XT1_Start(unsigned int xtdrive)
{
// Check if drive value is the expected one
if ((UCSCTL6 & XT1DRIVE_3) != xtdrive) {
UCSCTL6 &= ~XT1DRIVE_3; // Clear XT1drive field
UCSCTL6 |= xtdrive; // Set requested value
}
UCSCTL6 &= ~XT1OFF; // Enable XT1
UCSCTL6 |= XTS; // Enable HF mode
while (SFRIFG1 & OFIFG) { // Check OFIFG fault flag
UCSCTL7 &= ~(DCOFFG+XT1LFOFFG+XT1HFOFFG+XT2OFFG); // Clear OSC flaut Flags
SFRIFG1 &= ~OFIFG; // Clear OFIFG fault flag
}
}
unsigned int XT1_Start_Timeout(unsigned int xtdrive, unsigned int timeout)
{
// Check if drive value is the expected one
if ((UCSCTL6 & XT1DRIVE_3) != xtdrive) {
UCSCTL6 &= ~XT1DRIVE_3; // Clear XT1drive field
UCSCTL6 |= xtdrive; // Set requested value
}
UCSCTL6 &= ~XT1OFF; // Enable XT1
UCSCTL6 |= XTS; // Enable HF mode
while ((SFRIFG1 & OFIFG) && timeout--) { // Check OFIFG fault flag
UCSCTL7 &= ~(DCOFFG+XT1LFOFFG+XT1HFOFFG+XT2OFFG); // Clear OSC flaut Flags
SFRIFG1 &= ~OFIFG; // Clear OFIFG fault flag
}
if (timeout) {
return UCS_STATUS_OK;
}
else {
return UCS_STATUS_ERROR;
}
}
void XT1_Bypass(void)
{
UCSCTL6 |= XT1BYPASS;
while (SFRIFG1 & OFIFG) { // Check OFIFG fault flag
UCSCTL7 &= ~(DCOFFG+XT1LFOFFG+XT1HFOFFG+XT2OFFG); // Clear OSC flaut Flags
SFRIFG1 &= ~OFIFG; // Clear OFIFG fault flag
}
}
#endif
void XT1_Stop(void)
{
UCSCTL6 |= XT1OFF; // Switch off XT1 oscillator
}
#if 0
void XT2_Start(unsigned int xtdrive)
{
// Check if drive value is the expected one
if ((UCSCTL6 & XT2DRIVE_3) != xtdrive) {
UCSCTL6 &= ~XT2DRIVE_3; // Clear XT2drive field
UCSCTL6 |= xtdrive; // Set requested value
}
UCSCTL6 &= ~XT2OFF;
while (SFRIFG1 & OFIFG) { // Check OFIFG fault flag
UCSCTL7 &= ~(DCOFFG+XT1LFOFFG+XT1HFOFFG+XT2OFFG); // Clear OSC flaut Flags
SFRIFG1 &= ~OFIFG; // Clear OFIFG fault flag
}
}
unsigned int XT2_Start_Timeout(unsigned int xtdrive, unsigned int timeout)
{
// Check if drive value is the expected one
if ((UCSCTL6 & XT2DRIVE_3) != xtdrive) {
UCSCTL6 &= ~XT2DRIVE_3; // Clear XT2drive field
UCSCTL6 |= xtdrive; // Set requested value
}
UCSCTL6 &= ~XT2OFF;
while ((SFRIFG1 & OFIFG) && timeout--) { // Check OFIFG fault flag
UCSCTL7 &= ~(DCOFFG+XT1LFOFFG+XT1HFOFFG+XT2OFFG); // Clear OSC flaut Flags
SFRIFG1 &= ~OFIFG; // Clear OFIFG fault flag
}
if (timeout) {
return UCS_STATUS_OK;
}
else {
return UCS_STATUS_ERROR;
}
}
void XT2_Bypass(void)
{
#ifdef XT2BYPASS // On devices without XT2 this function will be empty
UCSCTL6 |= XT2BYPASS;
while (SFRIFG1 & OFIFG) { // Check OFIFG fault flag
UCSCTL7 &= ~(DCOFFG+XT1LFOFFG+XT1HFOFFG+XT2OFFG); // Clear OSC flaut Flags
SFRIFG1 &= ~OFIFG; // Clear OFIFG fault flag
}
#endif
}
void XT2_Stop(void)
{
UCSCTL6 |= XT2OFF; // Switch off XT2 oscillator
}
#endif
void Init_FLL_Settle(unsigned int fsystem, unsigned int ratio)
{
volatile unsigned int x;
// x = ratio * 32;
x = ratio << 5;
Init_FLL(fsystem, ratio);
/* from changes in Init_FLL we know that fll is now enabled */
while (x--) {
__delay_cycles(30);
}
}
static void Init_FLL(unsigned int fsystem, unsigned int ratio)
{
unsigned int d, dco_div_bits;
unsigned int mode;
#if 0
unsigned int srRegisterState;
#endif
mode = 0;
/* we only run this at startup and we want the fll enabled on exit */
#if 0
// Save actual state of FLL loop control, then disable it. This is needed to
// prevent the FLL from acting as we are making fundamental modifications to
// the clock setup.
srRegisterState = __get_SR_register() & SCG0;
#endif
d = ratio;
dco_div_bits = FLLD__2; // Have at least a divider of 2
if (fsystem > 16000) {
d >>= 1 ;
mode = 1;
}
else {
fsystem <<= 1; // fsystem = fsystem * 2
}
while (d > 512) {
dco_div_bits = dco_div_bits + FLLD0; // Set next higher div level
d >>= 1;
}
// Disable FLL
__bis_SR_register(SCG0);
UCSCTL0 = 0x0000; // Set DCO to lowest Tap
UCSCTL2 &= ~(0x03FF); // Reset FN bits
UCSCTL2 = dco_div_bits | (d - 1);
if (fsystem <= 630) // fsystem < 0.63MHz
UCSCTL1 = DCORSEL_0;
else if (fsystem < 1250) // 0.63MHz < fsystem < 1.25MHz
UCSCTL1 = DCORSEL_1;
else if (fsystem < 2500) // 1.25MHz < fsystem < 2.5MHz
UCSCTL1 = DCORSEL_2;
else if (fsystem < 5000) // 2.5MHz < fsystem < 5MHz
UCSCTL1 = DCORSEL_3;
else if (fsystem < 10000) // 5MHz < fsystem < 10MHz
UCSCTL1 = DCORSEL_4;
else if (fsystem < 20000) // 10MHz < fsystem < 20MHz
UCSCTL1 = DCORSEL_5;
else if (fsystem < 40000) // 20MHz < fsystem < 40MHz
UCSCTL1 = DCORSEL_6;
else
UCSCTL1 = DCORSEL_7;
// Re-enable FLL
__bic_SR_register(SCG0);
while (SFRIFG1 & OFIFG) { // Check OFIFG fault flag
UCSCTL7 &= ~(DCOFFG+XT1LFOFFG+XT1HFOFFG+XT2OFFG); // Clear OSC flaut Flags
SFRIFG1 &= ~OFIFG; // Clear OFIFG fault flag
}
/* Init fll is only run at startup - We want the fll enabled when
* this function is complete (so don't save a restore setting)
*/
#if 0
// Restore previous SCG0
__bis_SR_register(srRegisterState);
#endif
if (mode == 1) { // fsystem > 16000
SELECT_MCLK_SMCLK(SELM__DCOCLK + SELS__DCOCLK); // Select DCOCLK
}
else {
SELECT_MCLK_SMCLK(SELM__DCOCLKDIV + SELS__DCOCLKDIV); // Select DCODIVCLK
}
}

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HAL_UCS.o: F5xx_F6xx_Core_Lib/HAL_UCS.c \
/opt/msp430/lib/gcc/msp430/4.7.0/../../../../msp430/include/msp430.h \
/opt/msp430/lib/gcc/msp430/4.7.0/../../../../msp430/include/msp430f5438a.h \
/opt/msp430/lib/gcc/msp430/4.7.0/../../../../msp430/include/iomacros.h \
/opt/msp430/lib/gcc/msp430/4.7.0/../../../../msp430/include/in430.h \
/opt/msp430/lib/gcc/msp430/4.7.0/../../../../msp430/include/intrinsics.h \
F5xx_F6xx_Core_Lib/HAL_UCS.h F5xx_F6xx_Core_Lib/HAL_MACROS.h

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/*******************************************************************************
*
* HAL_UCS.h
* Provides Functions to Initialize the UCS/FLL and clock sources
*
*
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Created: Version 1.0 11/24/2009
* Updated: Version 2.0 12/15/2010
* Added Functions: XT2_Stop() and XT1_Stop()
*
******************************************************************************/
#ifndef HAL_UCS_H
#define HAL_UCS_H
#include "HAL_MACROS.h"
/*******************************************************************************
* Macros
******************************************************************************/
/* Select source for FLLREF e.g. SELECT_FLLREF(SELREF__XT1CLK) */
#define SELECT_FLLREF(source) st(UCSCTL3 = (UCSCTL3 & ~(SELREF_7)) | (source);)
/* Select source for ACLK e.g. SELECT_ACLK(SELA__XT1CLK) */
#define SELECT_ACLK(source) st(UCSCTL4 = (UCSCTL4 & ~(SELA_7)) | (source);)
/* Select source for MCLK e.g. SELECT_MCLK(SELM__XT2CLK) */
#define SELECT_MCLK(source) st(UCSCTL4 = (UCSCTL4 & ~(SELM_7)) | (source);)
/* Select source for SMCLK e.g. SELECT_SMCLK(SELS__XT2CLK) */
#define SELECT_SMCLK(source) st(UCSCTL4 = (UCSCTL4 & ~(SELS_7)) | (source);)
/* Select source for MCLK and SMCLK e.g. SELECT_MCLK_SMCLK(SELM__DCOCLK + SELS__DCOCLK) */
#define SELECT_MCLK_SMCLK(sources) st(UCSCTL4 = (UCSCTL4 & ~(SELM_7 + SELS_7)) | (sources);)
/* set ACLK/x */
#define ACLK_DIV(x) st(UCSCTL5 = (UCSCTL5 & ~(DIVA_7)) | (DIVA__##x);)
/* set MCLK/x */
#define MCLK_DIV(x) st(UCSCTL5 = (UCSCTL5 & ~(DIVM_7)) | (DIVM__##x);)
/* set SMCLK/x */
#define SMCLK_DIV(x) st(UCSCTL5 = (UCSCTL5 & ~(DIVS_7)) | (DIVS__##x);)
/* Select divider for FLLREF e.g. SELECT_FLLREFDIV(2) */
#define SELECT_FLLREFDIV(x) st(UCSCTL3 = (UCSCTL3 & ~(FLLREFDIV_7))|(FLLREFDIV__##x);)
/*******************************************************************************
* Defines
******************************************************************************/
#define UCS_STATUS_OK 0
#define UCS_STATUS_ERROR 1
#if 0
/*******************************************************************************
* \brief Startup routine for 32kHz Crystal on LFXT1
*
* \param xtdrive Bits defining the LFXT drive mode after startup
******************************************************************************/
extern void LFXT_Start(unsigned int xtdrive);
#endif
/*******************************************************************************
* \brief Startup routine for 32kHz Crystal on LFXT1 with timeout counter
*
* \param xtdrive Bits defining the LFXT drive mode after startup
* \param timeout Value for the timeout counter
******************************************************************************/
extern unsigned int LFXT_Start_Timeout(unsigned int xtdrive, unsigned int timeout);
#if 0
/*******************************************************************************
* \brief Startup routine for XT1
*
* \param xtdrive Bits defining the XT drive mode
******************************************************************************/
extern void XT1_Start(unsigned int xtdrive);
/*******************************************************************************
* \brief Startup routine for XT1 with timeout counter
*
* \param xtdrive Bits defining the XT drive mode
* \param timeout Value for the timeout counter
******************************************************************************/
extern unsigned int XT1_Start_Timeout(unsigned int xtdrive, unsigned int timeout);
/*******************************************************************************
* \brief Use XT1 in Bypasss mode
******************************************************************************/
extern void XT1_Bypass(void);
#endif
/*******************************************************************************
* \brief Stop XT1 oscillator
******************************************************************************/
extern void XT1_Stop(void);
#if 0
/*******************************************************************************
* \brief Startup routine for XT2
*
* \param xtdrive Bits defining the XT drive mode
******************************************************************************/
extern void XT2_Start(unsigned int xtdrive);
/*******************************************************************************
* \brief Startup routine for XT2 with timeout counter
*
* \param xtdrive Bits defining the XT drive mode
* \param timeout Value for the timeout counter
******************************************************************************/
extern unsigned int XT2_Start_Timeout(unsigned int xtdrive, unsigned int timeout);
/*******************************************************************************
* \brief Use XT2 in Bypasss mode for MCLK
******************************************************************************/
extern void XT2_Bypass(void);
/*******************************************************************************
* \brief Stop XT2 oscillator
******************************************************************************/
extern void XT2_Stop(void);
#endif
/*******************************************************************************
* \brief Initializes FLL of the UCS and wait till settled before allowing
* code execution to resume. The use of this function is preferred
* over the use of Init_FLL().
*
* \param fsystem Required system frequency (MCLK) in kHz
* \param ratio Ratio between fsystem and FLLREFCLK
******************************************************************************/
extern void Init_FLL_Settle(unsigned int fsystem, unsigned int ratio);
#endif /* HAL_UCS_H */

138
metawatch/Makefile Normal file
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#
# Makefile for msp430
# adapted from the example Makefile from the mspgcc project
#
# 'make' builds everything
# 'make clean' deletes everything except source files and Makefile
# You need to set TARGET, MCU and SOURCES for your project.
# TARGET is the name of the executable file to be produced
# $(TARGET).elf $(TARGET).hex and $(TARGET).txt nad $(TARGET).map are all generated.
# The TXT file is used for BSL loading, the ELF can be used for JTAG use
#
TARGET = oswald_mw
MCU = msp430f5438a
MEMMODEL = -mmemory-model=huge -fdata-sections -ffunction-sections # -mdata-region=far
# -gdwarf-2 -fdata-sections -ffunction-sections
#MEMMODEL = -mmpy=16 -msr20 -md20 -gdwarf-2 -fdata-sections -ffunction-sections
# MEMMODEL = -mmemory-model=medium -misr20
#MEMMODEL = -mmemory-model=medium
#APPCONFIG = -DDIGITAL -DMW_DEVBOARD_V2
#APPCONFIG = -DDIGITAL -DMW_DEVBOARD_V2 -DWITH_BTSTACK
#APPCONFIG = -DDIGITAL -DMW_DEVBOARD_V2 -DCC256x_TRANSP
#APPCONFIG = -DDIGITAL -DMW_DIGITAL_V2 -DMW_DEBUG_UART
APPCONFIG = -DDIGITAL -DMW_DIGITAL_V2
#BTCC256x_SCRIPT = bluetooth_init_cc2560_2.44.c
BTCC256x_SCRIPT = bluetooth_init_cc2564_2.8.c
# List all the source files here
# eg if you have a source file foo.c then list it here
OSWALD_SRC = ../ui/oswald_main.c ../ui/oswald_screens.c \
../ui/oswald_watch_faces.c \
../ui/oswald_strings.c ../ui/calendar.c \
../ui/oswald_graphics.c ../ui/oswald_fonts.c \
../ui/embedvm.c
SOURCES = mw_main.c mw_uart.c mw_lcd.c mw_adc.c mw_bt.c \
mw_acc.c $(BTCC256x_SCRIPT) \
bt_hci.c bt_l2cap.c \
oswald_hal.c $(OSWALD_SRC) \
F5xx_F6xx_Core_Lib/HAL_PMM.c \
F5xx_F6xx_Core_Lib/HAL_UCS.c
# $(BT_SMALLTOOTH_SRC)
# $(BT_STACK_SRC) \
#BT_STACK_INC = -Ibtstack/ -Ibtstack/include/
#BT_SMALLTOOTH_INV = -IBluetooth/
# Include are located in the Include directory
#INCLUDES = $(BT_STACK_INC)
#INCLUDES = $(BT_SMALLTOOTH_INV)
INCLUDES = -I../ui/
# BUILDNO = \"\#$(shell cat .buildno)-$(shell date +%y%m%d)\"
BUILDNO = \"$(shell date +%y%m%d)-\#$(shell cat .buildno)\"
# Add or subtract whatever MSPGCC flags you want. There are plenty more
#######################################################################################
CFLAGS = -mmcu=$(MCU) $(MEMMODEL) -g -Os -Wall -Wunused $(INCLUDES) $(APPCONFIG) -DBUILDNO=$(BUILDNO)
ASFLAGS = -mmcu=$(MCU) $(MEMMODEL) -x assembler-with-cpp -Wa,-gstabs
LDFLAGS = -mmcu=$(MCU) $(MEMMODEL) -Wl,-gc-sections -Wl,-Map=$(TARGET).map
########################################################################################
CC = msp430-gcc
LD = msp430-ld
AR = msp430-ar
AS = msp430-gcc
GASP = msp430-gasp
NM = msp430-nm
OBJCOPY = msp430-objcopy
RANLIB = msp430-ranlib
STRIP = msp430-strip
SIZE = msp430-size
READELF = msp430-readelf
MAKETXT = srec_cat
CP = cp -p
RM = rm -f
MV = mv
########################################################################################
# the file which will include dependencies
DEPEND = $(SOURCES:.c=.d)
# all the object files
OBJECTS = $(SOURCES:.c=.o)
all: .buildno $(TARGET).elf $(TARGET).hex $(TARGET).txt
prog: $(TARGET).hex
mspdebug tilib -d /dev/ttyACM3 -v 2500 "prog $(TARGET).hex"
prog_watch: $(TARGET).hex
mspdebug rf2500 -v 2500 "prog $(TARGET).hex"
$(TARGET).elf: $(OBJECTS)
echo "Linking $@"
$(CC) $(OBJECTS) $(LDFLAGS) $(LIBS) -o $@
echo
echo ">>>> Size of Firmware <<<<"
$(SIZE) $(TARGET).elf
echo
%.hex: %.elf
$(OBJCOPY) -O ihex $< $@
%.txt: %.hex
$(MAKETXT) -O $@ -TITXT $< -I
unix2dos $(TARGET).txt
# The above line is required for the DOS based TI BSL tool to be able to read the txt file generated from linux/unix systems.
%.o: %.c
echo "Compiling $<"
$(CC) -c $(CFLAGS) -o $@ $<
# rule for making assembler source listing, to see the code
%.lst: %.c
$(CC) -c $(ASFLAGS) -Wa,-anlhd $< > $@
# include the dependencies unless we're going to clean, then forget about them.
ifneq ($(MAKECMDGOALS), clean)
-include $(DEPEND)
endif
# dependencies file
# includes also considered, since some of these are our own
# (otherwise use -MM instead of -M)
%.d: %.c
echo "Generating dependencies $@ from $<"
$(CC) -M ${CFLAGS} $< >$@
#.SILENT:
.PHONY: clean
clean:
-$(RM) $(OBJECTS)
-$(RM) $(TARGET).*
-$(RM) $(SOURCES:.c=.lst)
-$(RM) $(DEPEND)
.buildno: $(OBJECTS)
@if ! test -f .buildno; then echo 0 > .buildno; fi
@echo $$(($$(cat .buildno) + 1)) > .buildno

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To compile basically just type "make".
Have a look into the Makefile for configurable options, like watch type,
Bluetooth firmware version etc.

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CC2560_BT_SP_BTS/bluetooth_init_cc2560_2.44.bts

File diff suppressed because it is too large Load diff

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CC2564_BT_BLE_SP_BTS/bluetooth_init_cc2564_2.8.bts

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#ifndef _BT_CC2560_H
#define _BT_CC2560_H
/* the init/patch script for CC256x chipset */
/* see TI license for details */
extern const uint8_t cc256x_init_script[];
extern const uint8_t cc256x_init_script_2[];
extern const uint32_t cc256x_init_script_size;
extern const char *cc256x_version;
#endif

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#include <msp430.h>
#include <msp430xgeneric.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include "mw_main.h"
#include "mw_uart.h"
#include "mw_bt.h"
#include "bt_hci.h"
#include "bt_l2cap.h"
static uint8_t local_bdaddr[6];
uint8_t *bt_hci_get_local_bdaddr(void)
{
return local_bdaddr;
}
static void bt_print_bd_addr(uint8_t *bd_addr)
{
#if defined MW_DEVBOARD_V2
int i;
char nums[4];
for (i=5; i>=0; i--) {
snprintf(nums, 4, "%02x", bd_addr[i]);
debug_uart_tx(nums);
if (i>0)
debug_uart_tx_char(':');
}
#endif
}
void bt_hci_process_acl_packet(unsigned char *packet)
{
#if defined MW_DEVBOARD_V2
char tstr[32];
#endif
uint16_t dlen;
uint16_t handle;
L2CAP_PB_FLAG PB;
L2CAP_BC_FLAG BC;
uint16_t channel;
uint16_t mlen;
// debug_uart_tx("ACL packet, ");
handle = packet[0] | ((packet[1] & 0x0f) << 8);
// snprintf(tstr, 32, "handle 0x%04x ", handle);
// debug_uart_tx(tstr);
PB = (packet[1] >> 4) & 0x03;
BC = (packet[1] >> 6) & 0x03;
// snprintf(tstr, 32, "PB 0x%02x BC 0x%02x ", PB, BC);
// debug_uart_tx(tstr);
dlen = packet[2] | ((uint16_t)packet[3] << 8);
// snprintf(tstr, 32, "len 0x%04x \n", dlen);
// debug_uart_tx(tstr);
// debug_dump_hex(dlen+4, packet);
channel = packet[4+2] | (packet[4+3] << 8);
mlen = packet[4] | (packet[4+1] << 8);
switch (channel) {
case L2CAP_CID_SIGNALING:
bt_l2cap_proc_signalling(handle, (packet+8), mlen);
break;
case L2CAP_CID_CONNECTIONLESS_CHANNEL:
break;
case L2CAP_CID_ATTRIBUTE_PROTOCOL:
break;
case L2CAP_CID_SIGNALING_LE:
break;
case L2CAP_CID_SECURITY_MANAGER_PROTOCOL:
break;
default:
if (channel > 0x3f) {
// just for sure, add a 0 as string delimiter
packet[mlen+8] = 0x00;
bt_l2cap_proc_dyn_channel(channel, handle, (packet+8), mlen);
} else {
#if defined MW_DEVBOARD_V2
snprintf(tstr, 32, "L2CAP unhandled CID 0x%04x\n", channel);
debug_uart_tx(tstr);
#endif
}
break;
}
}
void bt_hci_process_event_packet(unsigned char *packet)
{
#if defined MW_DEVBOARD_V2
char tstr[32];
#endif
int i;
// uint8_t bd_addr[6];
uint32_t dev_type;
// debug_uart_tx("Event packet, ");
// snprintf(tstr, 32, "evt 0x%02x: ", packet[0]);
// debug_uart_tx(tstr);
switch (packet[0]) {
case HCI_EVENT_INQUIRY_COMPLETE:
debug_uart_tx("inq complete\n");
break;
case HCI_EVENT_INQUIRY_RESULT:
debug_uart_tx("inq result\n");
break;
case HCI_EVENT_CONNECTION_COMPLETE:
debug_uart_tx("con complete from ");
#if defined MW_DEVBOARD_V2
bt_print_bd_addr((packet+5));
snprintf(tstr, 32, " status 0x%02x handle 0x%02x", packet[2], packet[3]);
debug_uart_tx(tstr);
snprintf(tstr, 32, " type 0x%02x enc 0x%02x\n", packet[11], packet[12]);
debug_uart_tx(tstr);
if (packet[2] == 0x00)
debug_uart_tx("connection established\n");
else
debug_uart_tx("connection failed\n");
#endif
break;
case HCI_EVENT_CONNECTION_REQUEST: {
uint8_t bd_addr[7];
switch (packet[11]) {
case HCI_LINK_TYPE_SCO:
debug_uart_tx("SCO");
break;
case HCI_LINK_TYPE_ACL:
debug_uart_tx("ACL");
break;
case HCI_LINK_TYPE_ESCO:
debug_uart_tx("eSCO");
break;
default:
debug_uart_tx("unknown type");
break;
}
debug_uart_tx(" con req from ");
for (i=0; i<6; i++) {
bd_addr[i] = packet[i+2];
}
bt_print_bd_addr(bd_addr);
dev_type = (uint32_t)packet[8] << 16;
dev_type |= (uint32_t)packet[9] << 8;
dev_type |= packet[10];
#if defined MW_DEVBOARD_V2
snprintf(tstr, 32, " rem. dtype 0x%06lx\n", dev_type);
debug_uart_tx(tstr);
#endif
//memcpy(tstr, bd_addr, 6);
//tstr[6] = 0x01; /* remain slave */
bd_addr[6] = 0x01; /* remain slave */
bt_hci_cmd(HCI_LINK_CTRL_OGF, HCI_ACCEPT_CONN_REQ_OCF, 7, bd_addr);
} break;
case HCI_EVENT_DISCONNECTION_COMPLETE:
debug_uart_tx("discon complete\n");
break;
case HCI_EVENT_AUTHENTICATION_COMPLETE_EVENT:
debug_uart_tx("auth complete\n");
break;
case HCI_EVENT_REMOTE_NAME_REQUEST_COMPLETE:
debug_uart_tx("rem name req complete\n");
break;
case HCI_EVENT_ENCRYPTION_CHANGE:
debug_uart_tx("enc change\n");
break;
case HCI_EVENT_CHANGE_CONNECTION_LINK_KEY_COMPLETE:
debug_uart_tx("change con link key complete\n");
break;
case HCI_EVENT_MASTER_LINK_KEY_COMPLETE:
debug_uart_tx("master link key complete\n");
break;
case HCI_EVENT_READ_REMOTE_SUPPORTED_FEATURES_COMPLETE:
debug_uart_tx("read rem feat. complete\n");
break;
case HCI_EVENT_READ_REMOTE_VERSION_INFORMATION_COMPLETE:
debug_uart_tx("read rem version complete\n");
break;
case HCI_EVENT_QOS_SETUP_COMPLETE:
debug_uart_tx("qos setup complete\n");
break;
case HCI_EVENT_COMMAND_COMPLETE:
// snprintf(tstr, 32, "%d cmd(s) complete: 0x%02x%02x=%d", packet[2], packet[3], packet[4], packet[5]);
// debug_uart_tx(tstr);
if (packet[2] > 0 &&
packet[3] == ((HCI_R_BD_ADDR_OCF | (HCI_INFO_PARAM_OGF << 10)) & 0xff) &&
packet[4] == (((HCI_R_BD_ADDR_OCF | (HCI_INFO_PARAM_OGF << 10)) & 0xff00) >> 8)) { // read local bdaddr
memcpy(local_bdaddr, (packet+6), 6);
#if defined MW_DEVBOARD_V2
debug_uart_tx("local bdaddr = ");
bt_print_bd_addr((uint8_t *)(packet+6));
debug_uart_tx("\n");
#endif
}
break;
case HCI_EVENT_COMMAND_STATUS:
debug_uart_tx("cmd status\n");
break;
case HCI_EVENT_HARDWARE_ERROR:
#if defined MW_DEVBOARD_V2
debug_uart_tx("hardw err");
snprintf(tstr, 32, " 0x%02x\n", packet[2]);
debug_uart_tx(tstr);
#endif
break;
case HCI_EVENT_FLUSH_OCCURED:
debug_uart_tx("flush occured\n");
break;
case HCI_EVENT_ROLE_CHANGE:
debug_uart_tx("role change\n");
break;
case HCI_EVENT_NUMBER_OF_COMPLETED_PACKETS:
debug_uart_tx("numb compl. packets\n");
break;
case HCI_EVENT_MODE_CHANGE_EVENT:
debug_uart_tx("mode change\n");
break;
case HCI_EVENT_RETURN_LINK_KEYS:
debug_uart_tx("return link keys\n");
break;
case HCI_EVENT_PIN_CODE_REQUEST:
debug_uart_tx("pin code request\n");
#if defined MW_DEVBOARD_V2
debug_uart_tx("from ");
bt_print_bd_addr((uint8_t *)(packet+2));
debug_uart_tx("\n");
#endif
memmove(packet, (packet+2), 6);
packet[6] = 0x04; // PIN has length of 4
memcpy((packet+7), BT_PIN, 4);
packet[7] = '4';
packet[8] = '3';
packet[9] = '1';
packet[10] = '2';
bt_hci_cmd(HCI_LINK_CTRL_OGF, HCI_PIN_CODE_REQ_REP_OCF, 11, packet);
break;
case HCI_EVENT_LINK_KEY_REQUEST:
debug_uart_tx("link key request\n");
break;
case HCI_EVENT_LINK_KEY_NOTIFICATION:
debug_uart_tx("link key notify\n");
break;
case HCI_EVENT_DATA_BUFFER_OVERFLOW:
debug_uart_tx("evt data buf overflow\n");
break;
case HCI_EVENT_MAX_SLOTS_CHANGED:
debug_uart_tx("max slots changed\n");
break;
case HCI_EVENT_READ_CLOCK_OFFSET_COMPLETE:
debug_uart_tx("read clock offset compl.\n");
break;
case HCI_EVENT_PACKET_TYPE_CHANGED:
debug_uart_tx("packet type changed\n");
break;
case HCI_EVENT_PAGE_SCAN_REPETION_MODE_CHANGE:
debug_uart_tx("page scan repetition mode changed\n");
break;
case HCI_EVENT_INQUIRY_RESULT_WITH_RSSI:
debug_uart_tx("inq result with RSSI\n");
break;
case HCI_EVENT_EXTENDED_INQUIRY_RESPONSE:
debug_uart_tx("ext. inq. resp.\n");
break;
case HCI_EVENT_LE_META:
debug_uart_tx("LE meta\n");
break;
case HCI_EVENT_VENDOR_SPECIFIC:
debug_uart_tx("vend. spec.\n");
break;
default:
debug_uart_tx("unknown\n");
break;
}
// debug_uart_tx("\n");
// for (i=2; i<=(packet[1]+1); i++) {
// snprintf(tstr, 32, " 0x%02x", packet[i]);
// debug_uart_tx(tstr);
// }
// debug_uart_tx("\n");
}
typedef enum {
HCI_PACKET_START = 0,
HCI_CMD_PACKET,
HCI_ACL_PACKET_HEADER,
HCI_ACL_PACKET_DATA,
HCI_SCO_PACKET,
HCI_EVENT_PACKET_HEADER,
HCI_EVENT_PACKET_DATA,
HCI_EHCILL_PACKET,
EHCILL_SLEEPING
} bt_hci_state_t;
static bt_hci_state_t state = HCI_PACKET_START;
unsigned char bt_feed_packet_data(unsigned char pdata)
{
char tstr[32];
static unsigned char packet[255];
static uint16_t bytes_left = 0;
static uint16_t pdata_pos = 0;
// snprintf(tstr, 32, "bt 0x%02x ", pdata);
// debug_uart_tx(tstr);
switch (state) {
case HCI_PACKET_START:
switch (pdata) {
case HCI_EVENT_PACKET:
state = HCI_EVENT_PACKET_HEADER;
bytes_left = 1;
pdata_pos = 0;
memset(packet, 0, 64);
break;
case HCI_ACL_DATA_PACKET:
state = HCI_ACL_PACKET_HEADER;
bytes_left = 3;
pdata_pos = 0;
memset(packet, 0, 64);
break;
case EHCILL_GO_TO_SLEEP_IND:
debug_uart_tx("eHCILL go to sleep ind\n");
state = HCI_PACKET_START;
// disable BT UART?
// mabye UCA1CTL1 = UCSWRST ?
pdata = EHCILL_GO_TO_SLEEP_ACK;
mw_bt_uart_tx(&pdata, 0x01);
// pull RTS -> stop data
BT_IO_POUT |= BT_IO_RTS;
// enable IRQ on CTS
P1IFG &= ~BT_IO_CTS;
P1IE |= BT_IO_CTS;
state = EHCILL_SLEEPING;
break;
case EHCILL_GO_TO_SLEEP_ACK:
debug_uart_tx("eHCILL go to sleep ack\n");
state = HCI_PACKET_START;
break;
case EHCILL_WAKE_UP_IND:
debug_uart_tx("eHCILL wake up ind\n");
state = HCI_PACKET_START;
break;
case EHCILL_WAKE_UP_ACK:
debug_uart_tx("eHCILL wake up ack\n");
state = HCI_PACKET_START;
break;
default:
debug_uart_tx("unexpected packet start\n");
break;
}
break;
case HCI_EVENT_PACKET_HEADER:
if (bytes_left != 0) {
packet[pdata_pos++] = pdata;
bytes_left--;
} else {
state = HCI_EVENT_PACKET_DATA;
packet[pdata_pos++] = pdata;
bytes_left = pdata;
}
break;
case HCI_EVENT_PACKET_DATA:
packet[pdata_pos++] = pdata;
bytes_left--;
if (bytes_left == 0) {
state = HCI_PACKET_START;
bt_hci_process_event_packet(packet);
}
break;
case HCI_ACL_PACKET_HEADER:
if (bytes_left != 0) {
packet[pdata_pos++] = pdata;
bytes_left--;
} else {
state = HCI_ACL_PACKET_DATA;
packet[pdata_pos] = pdata;
bytes_left = (packet[pdata_pos-1] | (packet[pdata_pos] << 8));
// snprintf(tstr, 32, "ACL data len 0x%04x\n", bytes_left);
// debug_uart_tx(tstr);
// snprintf(tstr, 32, "%d (0x%02x 0x%02x)\n", pdata_pos, packet[pdata_pos-1], packet[pdata_pos]);
// debug_uart_tx(tstr);
pdata_pos++;
}
break;
case HCI_ACL_PACKET_DATA:
// snprintf(tstr, 32, "%02x ", pdata);
// debug_uart_tx(tstr);
packet[pdata_pos++] = pdata;
bytes_left--;
if (bytes_left == 0) {
// debug_uart_tx("\n");
state = HCI_PACKET_START;
bt_hci_process_acl_packet(packet);
}
break;
default:
debug_uart_tx("hosed HCI state!\n");
snprintf(tstr, 32, " state = %d\n", state);
debug_uart_tx(tstr);
break;
};
// one byte consumed
return 1;
}
typedef struct {
uint8_t type;
uint16_t cmd;
uint8_t length;
} __attribute__((packed)) bt_hci_cmd_t;
void bt_hci_cmd(const uint8_t OGF, const uint8_t OCF, const uint8_t data_len, const void *data)
{
bt_hci_cmd_t packet;
// refuse any HCI if interface is not enabled
if (mw_bt_is_enabled() == 0)
return;
if (state == EHCILL_SLEEPING) {
uint8_t ehcill_p = EHCILL_WAKE_UP_IND;
debug_uart_tx("wakeup HCILL\n");
state = HCI_PACKET_START;
mw_bt_uart_tx(&ehcill_p, 1);
__delay_cycles(300000);
BT_IO_POUT &= ~BT_IO_RTS; // drop RTS -> start data
}
packet.type = HCI_COMMAND_PACKET;
packet.cmd = OCF | (OGF<<10);
packet.length = data_len;
mw_bt_uart_tx(&packet, sizeof(bt_hci_cmd_t));
if (data_len > 0 && data != NULL)
mw_bt_uart_tx(data, data_len);
}
typedef struct {
uint16_t acl_handle;
uint16_t max_interval;
uint16_t min_interval;
uint16_t sniff_attempt;
uint16_t sniff_timeout;
} __attribute__((packed)) bt_hci_sniff_cmd_t;
void bt_hci_set_sniff_mode(const uint16_t acl_handle, const uint16_t max_interval, const uint16_t min_interval, const uint16_t sniff_attempt, const uint16_t sniff_timeout)
{
bt_hci_sniff_cmd_t sniff_cmd;
sniff_cmd.acl_handle = acl_handle;
sniff_cmd.max_interval = max_interval;
sniff_cmd.min_interval = min_interval;
sniff_cmd.sniff_attempt = sniff_attempt;
sniff_cmd.sniff_timeout = sniff_timeout;
bt_hci_cmd(HCI_LINK_POLICY_OGF, HCI_SNIFF_MODE_OCF, sizeof(sniff_cmd), &sniff_cmd);
}
typedef struct {
uint8_t type;
uint16_t handle;
uint16_t total_length;
uint16_t data_length;
uint16_t channel;
} __attribute__((packed)) bt_hci_acl_t;
void bt_acl_send(const uint16_t handle, const uint8_t PB, const uint8_t BC, const uint16_t channel, const uint16_t dlen, const void *dat)
{
bt_hci_acl_t packet;
// refuse any HCI if interface is not enabled
if (mw_bt_is_enabled() == 0)
return;
packet.type = HCI_ACL_DATA_PACKET;
packet.handle = handle | ((PB & 0x03) << 12) | ((BC & 0x03) << 14);
packet.total_length = dlen + 4;
packet.data_length = dlen;
packet.channel = channel;
mw_bt_uart_tx(&packet, sizeof(bt_hci_acl_t));
mw_bt_uart_tx(dat, dlen);
}
void bt_hci_init(void)
{
state = HCI_PACKET_START;
}
void bt_hci_ehcill_wake(void)
{
const uint8_t ehcill_p = EHCILL_WAKE_UP_ACK;
debug_uart_tx("HCILL wakeup\n");
P1IE &= ~BT_IO_CTS;
P1IFG &= ~BT_IO_CTS;
state = HCI_PACKET_START;
BT_IO_POUT &= ~BT_IO_RTS; // drop RTS -> start data
mw_bt_uart_tx(&ehcill_p, 1);
//__delay_cycles(160000);
}

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#ifndef _BT_HCI_H
#define _BT_HCI_H
/* HCI Command OGF */
#define HCI_LINK_CTRL_OGF 0x01
#define HCI_LINK_POLICY_OGF 0x02
#define HCI_HC_BB_OGF 0x03
#define HCI_INFO_PARAM_OGF 0x04
/* HCI Command OCF */
#define HCI_DISCONN_OCF 0x06
#define HCI_ACCEPT_CONN_REQ_OCF 0x09
#define HCI_RESET_OCF 0x03
#define HCI_W_SCAN_EN_OCF 0x1A
#define HCI_R_COD_OCF 0x23
#define HCI_W_COD_OCF 0x24
#define HCI_H_BUF_SIZE_OCF 0x33
#define HCI_H_NUM_COMPL_OCF 0x35
#define HCI_R_BUF_SIZE_OCF 0x05
#define HCI_R_BD_ADDR_OCF 0x09
#define HCI_W_LOCAL_NAME_OCF 0x13
#define HCI_PIN_CODE_REQ_REP_OCF 0x0D
#define HCI_R_STORED_LINK_KEY_OCF 0x0D
#define HCI_W_STORED_LINK_KEY_OCF 0x11
#define HCI_LINK_KEY_REQ_REP_OCF 0x0B
#define HCI_SNIFF_MODE_OCF 0x03
#define HCI_COMMAND_PACKET 0x01
#define HCI_ACL_DATA_PACKET 0x02
#define HCI_SCO_DATA_PACKET 0x03
#define HCI_EVENT_PACKET 0x04
#define HCI_EVENT_INQUIRY_COMPLETE 0x01
#define HCI_EVENT_INQUIRY_RESULT 0x02
#define HCI_EVENT_CONNECTION_COMPLETE 0x03
#define HCI_EVENT_CONNECTION_REQUEST 0x04
#define HCI_EVENT_DISCONNECTION_COMPLETE 0x05
#define HCI_EVENT_AUTHENTICATION_COMPLETE_EVENT 0x06
#define HCI_EVENT_REMOTE_NAME_REQUEST_COMPLETE 0x07
#define HCI_EVENT_ENCRYPTION_CHANGE 0x08
#define HCI_EVENT_CHANGE_CONNECTION_LINK_KEY_COMPLETE 0x09
#define HCI_EVENT_MASTER_LINK_KEY_COMPLETE 0x0A
#define HCI_EVENT_READ_REMOTE_SUPPORTED_FEATURES_COMPLETE 0x0B
#define HCI_EVENT_READ_REMOTE_VERSION_INFORMATION_COMPLETE 0x0C
#define HCI_EVENT_QOS_SETUP_COMPLETE 0x0D
#define HCI_EVENT_COMMAND_COMPLETE 0x0E
#define HCI_EVENT_COMMAND_STATUS 0x0F
#define HCI_EVENT_HARDWARE_ERROR 0x10
#define HCI_EVENT_FLUSH_OCCURED 0x11
#define HCI_EVENT_ROLE_CHANGE 0x12
#define HCI_EVENT_NUMBER_OF_COMPLETED_PACKETS 0x13
#define HCI_EVENT_MODE_CHANGE_EVENT 0x14
#define HCI_EVENT_RETURN_LINK_KEYS 0x15
#define HCI_EVENT_PIN_CODE_REQUEST 0x16
#define HCI_EVENT_LINK_KEY_REQUEST 0x17
#define HCI_EVENT_LINK_KEY_NOTIFICATION 0x18
#define HCI_EVENT_DATA_BUFFER_OVERFLOW 0x1A
#define HCI_EVENT_MAX_SLOTS_CHANGED 0x1B
#define HCI_EVENT_READ_CLOCK_OFFSET_COMPLETE 0x1C
#define HCI_EVENT_PACKET_TYPE_CHANGED 0x1D
#define HCI_EVENT_PAGE_SCAN_REPETION_MODE_CHANGE 0x20
#define HCI_EVENT_INQUIRY_RESULT_WITH_RSSI 0x22
#define HCI_EVENT_EXTENDED_INQUIRY_RESPONSE 0x2F
#define HCI_EVENT_LE_META 0x3E
#define HCI_EVENT_VENDOR_SPECIFIC 0xFF
#define HCI_SUBEVENT_LE_CONNECTION_COMPLETE 0x01
#define HCI_SUBEVENT_LE_ADVERTISING_REPORT 0x02
#define HCI_SUBEVENT_LE_CONNECTION_UPDATE_COMPLETE 0x03
#define HCI_SUBEVENT_LE_READ_REMOTE_USED_FEATURES_COMPLETE 0x04
#define HCI_SUBEVENT_LE_LONG_TERM_KEY_REQUEST 0x05
#define HCI_LINK_TYPE_SCO 0x00
#define HCI_LINK_TYPE_ACL 0x01
#define HCI_LINK_TYPE_ESCO 0x02
#define HCI_BB_SCAN_NOSCAN 0x00
#define HCI_BB_SCAN_INQUIRY 0x01
#define HCI_BB_SCAN_PAGE 0x02
/* CC256x specific eHCILL */
#define EHCILL_GO_TO_SLEEP_IND 0x30
#define EHCILL_GO_TO_SLEEP_ACK 0x31
#define EHCILL_WAKE_UP_IND 0x32
#define EHCILL_WAKE_UP_ACK 0x33
#define BT_PIN "4312"
void bt_hci_init(void);
void bt_hci_cmd(const uint8_t OGF, const uint8_t OCF, const uint8_t data_len, const void *data);
void bt_hci_set_sniff_mode(const uint16_t acl_handle, const uint16_t max_interval, const uint16_t min_interval, const uint16_t sniff_attempt, const uint16_t sniff_timeout);
void bt_acl_send(const uint16_t handle, const uint8_t PB, const uint8_t BC, const uint16_t channel, const uint16_t len, const void *dat);
uint8_t *bt_hci_get_local_bdaddr(void);
void bt_hci_ehcill_wake(void);
#endif

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#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include "mw_uart.h"
#include "mw_bt.h"
#include "bt_hci.h"
#include "bt_l2cap.h"
#include "oswald_main.h"
static bt_l2cap_con_t _l2cap_con;
void init_l2cap(void)
{
memset(&_l2cap_con, 0, sizeof(bt_l2cap_con_t));
}
void bt_l2cap_proc_dyn_channel(const uint16_t channel, const uint16_t handle, const void *mdat, uint16_t mlen)
{
if (channel == _l2cap_con.locCID) {
debug_uart_tx("L2CAP data rcvd: ");
debug_dump_ascii(mlen, mdat);
if (_l2cap_con.PSM == 0x1001) {
oswald_handle_comm_input(mlen, mdat);
} else if (_l2cap_con.PSM == 0x0001) { // SDP
debug_uart_tx("SDP req: ");
debug_dump_hex(mlen, mdat);
} else
debug_uart_tx("L2CAP data on unhandled PSM\n");
} else {
debug_uart_tx("L2CAP CID does not match local CID\n");
}
}
uint8_t bt_l2cap_get_connected(const uint16_t channel)
{
if (_l2cap_con.locCID == channel)
return _l2cap_con.cstate;
else
return BT_L2CAP_CON_IDLE;
}
void bt_l2cap_send_channel(const uint16_t channel, const void *mdat, uint16_t mlen)
{
if (_l2cap_con.cstate == BT_L2CAP_CON_CONNECTED && _l2cap_con.hci_handle != 0 && _l2cap_con.remCID != 0 &&
mlen != 0 && mdat != NULL) {
bt_acl_send(_l2cap_con.hci_handle, PB_FIRST_FLUSHABLE, BC_NO_BROADCAST, _l2cap_con.remCID, mlen, mdat);
}
}
typedef struct {
uint8_t resp;
uint8_t ident;
uint16_t length;
uint16_t DCID;
uint16_t SCID;
} __attribute__((packed)) bt_l2cap_disconn_resp_t;
typedef struct {
uint8_t resp;
uint8_t ident;
uint16_t length;
uint16_t SCID;
uint16_t flags;
uint16_t result;
uint16_t config;
} __attribute__((packed)) bt_l2cap_conf_resp_t;
void bt_l2cap_proc_signalling(const uint16_t handle, unsigned char *mdat, uint16_t mlen)
{
#if defined MW_DEVBOARD_V2
char tstr[16];
#endif
debug_uart_tx("ACL L2CAP signalling ");
switch (mdat[0]) {
case COMMAND_REJECT:
debug_uart_tx("command reject\n");
break;
case CONNECTION_REQUEST: {
uint8_t ident = mdat[1];
uint16_t PSM = mdat[4] | (mdat[5] << 8);;
uint16_t src_CID = mdat[6] | (mdat[7] << 8);;
#if defined MW_DEVBOARD_V2
debug_uart_tx("connection request on ");
snprintf(tstr, 16, "PSM 0x%04x ", PSM);
debug_uart_tx(tstr);
snprintf(tstr, 16, "srcCID 0x%04x\n", src_CID);
debug_uart_tx(tstr);
#endif
bt_l2cap_handle_connection_request(handle, ident, PSM, src_CID);
} break;
case CONNECTION_RESPONSE:
debug_uart_tx("connection response\n");
break;
case CONFIGURE_REQUEST: {
uint8_t ident = mdat[1];
uint16_t len = mdat[2] | (mdat[3] << 8);
uint16_t dst_CID = mdat[4] | (mdat[5] << 8);
uint16_t flags = mdat[6] | (mdat[7] << 8);
bt_l2cap_conf_resp_t resp;
#if defined MW_DEVBOARD_V2
debug_uart_tx("configure request ");
snprintf(tstr, 16, "len 0x%04x ", len);
debug_uart_tx(tstr);
snprintf(tstr, 16, "DCID 0x%04x ", dst_CID);
debug_uart_tx(tstr);
snprintf(tstr, 16, "flags 0x%04x\n", flags);
debug_uart_tx(tstr);
#if 0
for (i=8; i<((len-4)+8); i++) {
snprintf(tstr, 16, "0x%02x ", mdat[i]);
debug_uart_tx(tstr);
}
debug_uart_tx("\n");
#endif
debug_dump_hex(len-4+8, (mdat+8));
#endif
resp.resp = CONFIGURE_RESPONSE;
resp.ident = ident;
resp.length = 0x06;
if (dst_CID != _l2cap_con.locCID)
debug_uart_tx("warning: DCID does not match\n");
resp.SCID = _l2cap_con.remCID;
resp.flags = flags;
resp.result = 0x0000; // success
resp.config = 0x0000; // OK?
bt_acl_send(handle, PB_FIRST_FLUSHABLE, BC_NO_BROADCAST, L2CAP_CID_SIGNALING, sizeof(bt_l2cap_conf_resp_t)-2, &resp);
} break;
case CONFIGURE_RESPONSE:
debug_uart_tx("configure response\n");
break;
case DISCONNECTION_REQUEST: {
bt_l2cap_disconn_resp_t resp;
uint8_t ident = mdat[1];
uint16_t dst_CID = mdat[4] | (mdat[5] << 8);
uint16_t src_CID = mdat[6] | (mdat[7] << 8);
debug_uart_tx("disconnect request\n");
if (dst_CID != _l2cap_con.locCID || src_CID != _l2cap_con.remCID)
debug_uart_tx("warning: discon on unknown CID\n");
resp.resp = DISCONNECTION_RESPONSE;
resp.ident = ident;
resp.length = 0x0004;
resp.DCID = _l2cap_con.locCID;
resp.SCID = _l2cap_con.remCID;
bt_acl_send(handle, PB_FIRST_FLUSHABLE, BC_NO_BROADCAST, L2CAP_CID_SIGNALING, sizeof(bt_l2cap_disconn_resp_t), &resp);
init_l2cap();
} break;
case DISCONNECTION_RESPONSE:
debug_uart_tx("disconnect response\n");
break;
case ECHO_REQUEST:
debug_uart_tx("echo request\n");
mdat[0] = ECHO_RESPONSE;
bt_acl_send(handle, PB_FIRST_FLUSHABLE, BC_NO_BROADCAST, L2CAP_CID_SIGNALING, mlen, mdat);
break;
case ECHO_RESPONSE:
debug_uart_tx("echo response\n");
break;
case INFORMATION_REQUEST: {
uint16_t info_type = mdat[4] | (mdat[5] << 8);
debug_uart_tx("information request ");
switch (info_type) {
case 0x0001:
debug_uart_tx("connectionless mtu\n");
break;
case 0x0002:
debug_uart_tx("ext. feat. support\n");
mdat[0] = INFORMATION_RESPONSE;
mdat[2] = 0x02;
mdat[3] = 0x00;
mdat[6] = 0x01; // not supported
mdat[7] = 0x00;
bt_acl_send(handle, PB_FIRST_FLUSHABLE, BC_NO_BROADCAST, L2CAP_CID_SIGNALING, 0x08, mdat);
break;
case 0x0003:
debug_uart_tx("fixed channel support\n");
break;
default:
debug_uart_tx("unknown\n");
break;
};
} break;
case INFORMATION_RESPONSE:
debug_uart_tx("information response\n");
break;
default:
debug_uart_tx("unknown\n");
break;
}
}
typedef struct {
uint8_t resp;
uint8_t ident;
uint16_t length;
uint16_t DCID;
uint16_t SCID;
uint16_t result;
uint16_t status;
} __attribute__((packed)) bt_l2cap_conn_resp_t;
typedef struct {
uint8_t resp;
uint8_t ident;
uint16_t length;
uint16_t DCID;
uint16_t flags;
uint8_t option;
uint8_t olen;
uint16_t odat;
} __attribute__((packed)) bt_l2cap_conf_req_t;
void bt_l2cap_handle_connection_request(const uint16_t handle, const uint8_t ident, const uint16_t PSM, const uint16_t src_CID)
{
bt_l2cap_conn_resp_t resp;
// for now we only support one connection, only on PSM 0x1001
if (_l2cap_con.cstate == BT_L2CAP_CON_IDLE && PSM == 0x1001) {
bt_l2cap_conf_req_t req;
_l2cap_con.cstate = BT_L2CAP_CON_CONNECTED;
_l2cap_con.hci_handle = handle;
_l2cap_con.PSM = PSM;
_l2cap_con.locCID = 0x0040;
_l2cap_con.remCID = src_CID;
_l2cap_con.locMTU = 0xf0;
_l2cap_con.remMTU = 0x00;
resp.resp = CONNECTION_RESPONSE;
resp.ident = ident;
resp.length = 0x0008;
resp.DCID = _l2cap_con.locCID;
resp.SCID = _l2cap_con.remCID;
resp.result = BT_L2CAP_CON_RES_SUCCESS;
resp.status = BT_L2CAP_CON_STAT_NOINFO;
debug_uart_tx("l2cap accepting connection\n");
bt_acl_send(handle, PB_FIRST_FLUSHABLE, BC_NO_BROADCAST, L2CAP_CID_SIGNALING, sizeof(bt_l2cap_conn_resp_t), &resp);
req.resp = CONFIGURE_REQUEST;
req.ident = ident;
req.length = 0x08;
req.DCID = _l2cap_con.remCID;
req.flags = 0x00;
req.option = 0x01; // MTU
req.olen = 0x02;
req.odat = _l2cap_con.locMTU;
bt_acl_send(handle, PB_FIRST_FLUSHABLE, BC_NO_BROADCAST, L2CAP_CID_SIGNALING, sizeof(bt_l2cap_conf_req_t), &req);
// max_interval Mandatory Range: 0x0006 to 0x0540
// min_interval Mandatory Range: 0x0006 to 0x0540
// sniff_attempt Mandatory Range for Controller: 1 to Tsniff/2
// sniff_timeout Mandatory Range for Controller: 0 to 0x0028
bt_hci_set_sniff_mode(handle, 0x10, 0x06, 0x20, 0x10);
} else {
resp.resp = CONNECTION_RESPONSE;
resp.ident = ident;
resp.length = 0x0008;
resp.DCID = 0x0000;
resp.SCID = src_CID;
resp.result = BT_L2CAP_CON_RES_REFUSED_RSRC;
resp.status = BT_L2CAP_CON_STAT_NOINFO;
debug_uart_tx("l2cap refusing connection\n");
bt_acl_send(handle, PB_FIRST_FLUSHABLE, BC_NO_BROADCAST, L2CAP_CID_SIGNALING, sizeof(bt_l2cap_conn_resp_t), &resp);
}
}

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#ifndef _BT_L2CAP_H
#define _BT_L2CAP_H
#define L2CAP_CID_SIGNALING 0x0001
#define L2CAP_CID_CONNECTIONLESS_CHANNEL 0x0002
#define L2CAP_CID_ATTRIBUTE_PROTOCOL 0x0004
#define L2CAP_CID_SIGNALING_LE 0x0005
#define L2CAP_CID_SECURITY_MANAGER_PROTOCOL 0x0006
typedef enum {
COMMAND_REJECT = 1,
CONNECTION_REQUEST,
CONNECTION_RESPONSE,
CONFIGURE_REQUEST,
CONFIGURE_RESPONSE,
DISCONNECTION_REQUEST,
DISCONNECTION_RESPONSE,
ECHO_REQUEST,
ECHO_RESPONSE,
INFORMATION_REQUEST,
INFORMATION_RESPONSE
} L2CAP_SIGNALING_COMMANDS;
typedef enum {
PB_FIRST_NON_FLUSH = 0,
PB_CONTINUE_FRAGMENT,
PB_FIRST_FLUSHABLE,
PB_COMPLETE_PDU
} L2CAP_PB_FLAG;
typedef enum {
BC_NO_BROADCAST = 0,
BC_ACTIVE_SLAVE,
BC_PARKED_SLAVE,
BC_RESERVED
} L2CAP_BC_FLAG;
// Connection result values
#define BT_L2CAP_CON_RES_SUCCESS 0x0000
#define BT_L2CAP_CON_RES_PENDING 0x0001
#define BT_L2CAP_CON_RES_REFUSED_PSM 0x0002
#define BT_L2CAP_CON_RES_REFUSED_SECURITY 0x0003
#define BT_L2CAP_CON_RES_REFUSED_RSRC 0x0004
#define BT_L2CAP_CON_STAT_NOINFO 0x0000
#define BT_L2CAP_CON_STAT_AUTHEN_PENDING 0x0001
#define BT_L2CAP_CON_STAT_AUTHOR_PENDING 0x0002
typedef enum {
BT_L2CAP_CON_IDLE = 0,
BT_L2CAP_CON_CONNECTED
} bt_l2cap_con_state_t;
// describes the L2CAP connection
typedef struct {
bt_l2cap_con_state_t cstate;
uint16_t hci_handle;
uint16_t PSM; // PSM of this connection
uint16_t locCID; // our local CID
uint16_t remCID; // remote host CID
uint16_t locMTU;
uint16_t remMTU;
} bt_l2cap_con_t;
void init_l2cap(void);
void bt_l2cap_proc_dyn_channel(const uint16_t channel, const uint16_t handle, const void *mdat, uint16_t mlen);
uint8_t bt_l2cap_get_connected(const uint16_t channel);
void bt_l2cap_send_channel(const uint16_t channel, const void *mdat, uint16_t mlen);
void bt_l2cap_proc_signalling(const uint16_t handle, unsigned char *mdat, uint16_t mlen);
void bt_l2cap_handle_connection_request(const uint16_t handle, const uint8_t ident, const uint16_t PSM, const uint16_t src_CID);
#endif

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calendar.o: calendar.c oswald.h \
/opt/msp430/lib/gcc/msp430/4.7.0/../../../../msp430/include/stdio.h \
/opt/msp430/lib/gcc/msp430/4.7.0/include/stddef.h \
/opt/msp430/lib/gcc/msp430/4.7.0/../../../../msp430/include/sys/types.h \
/opt/msp430/lib/gcc/msp430/4.7.0/../../../../msp430/include/sys/cdefs.h \
/opt/msp430/lib/gcc/msp430/4.7.0/../../../../msp430/include/sys/inttypes.h \
/opt/msp430/lib/gcc/msp430/4.7.0/../../../../msp430/include/inttypes.h \
/opt/msp430/lib/gcc/msp430/4.7.0/../../../../msp430/include/stdint.h \
/opt/msp430/lib/gcc/msp430/4.7.0/../../../../msp430/include/msp430libc.h \
/opt/msp430/lib/gcc/msp430/4.7.0/include/stdarg.h \
/opt/msp430/lib/gcc/msp430/4.7.0/../../../../msp430/include/string.h \
calendar.h

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//==============================================================================
// Copyright 2011 Meta Watch Ltd. - http://www.MetaWatch.org/
//
// Licensed under the Meta Watch License, Version 1.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.MetaWatch.org/licenses/license-1.0.html
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//==============================================================================
/******************************************************************************/
/*! \file hal_devboard_v2_defs.h
*
* Pin and peripheral definitions for Development Board Version 2
*/
/******************************************************************************/
#ifndef HAL_DEVBOARD_V2_DEFS_H
#define HAL_DEVBOARD_V2_DEFS_H
// Defines for the LCD display interface, single channel SPI output
#define LCD_5V_PDIR P4DIR
#define LCD_5V_POUT P4OUT
#define LCD_5V_BIT BIT0
#define ENABLE_LCD_POWER() { \
LCD_5V_PDIR |= LCD_5V_BIT; \
LCD_5V_POUT |= LCD_5V_BIT; \
}
#define DISABLE_LCD_POWER() { \
LCD_5V_PDIR |= LCD_5V_BIT; \
LCD_5V_POUT &= ~LCD_5V_BIT; \
}
#define LCD_ENABLE_PDIR ( P3DIR )
#define LCD_ENABLE_POUT ( P3OUT )
#define LCD_ENABLE_PIN ( BIT6 )
#define ENABLE_LCD_ENABLE() { \
LCD_ENABLE_PDIR |= LCD_ENABLE_PIN; \
LCD_ENABLE_POUT |= LCD_ENABLE_PIN; \
}
#define DISABLE_LCD_ENABLE() { \
LCD_ENABLE_PDIR |= LCD_ENABLE_PIN; \
LCD_ENABLE_POUT &= ~LCD_ENABLE_PIN; \
}
#define LCD_CS_PDIR ( P9DIR )
#define LCD_CS_POUT ( P9OUT )
#define LCD_CS_PIN ( BIT0 )
#define LCD_SPI_PORT_SEL ( P3SEL )
#define LCD_SPI_SIMO_BIT ( BIT1 )
#define LCD_SPI_CLK_BIT ( BIT3 )
#define LCD_SPI_SOMI_BIT ( BIT2 )
#define LCD_CS_ASSERT() { LCD_CS_POUT |= LCD_CS_PIN; }
#define LCD_CS_DEASSERT() { LCD_CS_POUT &= ~LCD_CS_PIN; }
#define CONFIG_LCD_PINS() { \
LCD_SPI_PORT_SEL |= LCD_SPI_SIMO_BIT; \
LCD_SPI_PORT_SEL |= LCD_SPI_CLK_BIT; \
LCD_SPI_PORT_SEL |= LCD_SPI_SOMI_BIT; \
ENABLE_LCD_ENABLE(); \
LCD_CS_PDIR |= LCD_CS_PIN; \
LCD_CS_DEASSERT(); \
}
// labeled EL_EN on schematic
#define LCD_LED_PDIR ( P4DIR )
#define LCD_LED_POUT ( P4OUT )
#define LCD_LED_PIN ( BIT4 )
#define DISABLE_LCD_LED() { \
LCD_LED_PDIR |= LCD_LED_PIN; \
LCD_LED_POUT &= ~LCD_LED_PIN; \
}
#define ENABLE_LCD_LED() { \
LCD_LED_PDIR |= LCD_LED_PIN; \
LCD_LED_POUT |= LCD_LED_PIN; \
}
#define LCD_SPI_UCBxCTL0 UCB0CTL0 // Control register
#define LCD_SPI_UCBxCTL1 UCB0CTL1 // Control register
#define LCD_SPI_UCBxBR0 UCB0BR0 // Baudrate prescale
#define LCD_SPI_UCBxBR1 UCB0BR1 // Baudrate divider
#define LCD_SPI_UCBxTXBUF UCB0TXBUF // Transmit buffer
#define LCD_SPI_UCBxRXBUF UCB0RXBUF // Receive buffer
#define LCD_SPI_UCBxIE UCB0IE // Interrupt enable register
#define LCD_SPI_UCBxIFG UCB0IFG // Interrupt flag register
#define LCD_SPI_UCBxIV UCB0IV // Interrupt vector register
#define LCD_SPI_UCBxSTAT UCB0STAT // status register
// Definitions for the OLED Display
// peripheral mapping for OLED
#define OLED_I2C_CTL0 ( UCB0CTL0 )
#define OLED_I2C_CTL1 ( UCB0CTL1 )
#define OLED_I2C_BR0 ( UCB0BR0 )
#define OLED_I2C_BR1 ( UCB0BR1 )
#define OLED_I2C_I2CSA ( UCB0I2CSA )
#define OLED_I2C_IE ( UCB0IE )
#define OLED_I2C_IFG ( UCB0IFG )
#define OLED_I2C_TXBUF ( UCB0TXBUF )
#define OLED_I2C_RXBUF ( UCB0RXBUF )
// interrupt mapping for OLED
#define USCI_OLED_I2C_VECTOR ( USCI_B0_VECTOR )
#define USCI_OLED_I2C_IV ( UCB0IV )
// OLED reset is active low
#define OLED_RSTN_PDIR ( P8DIR )
#define OLED_RSTN_POUT ( P8OUT )
#define OLED_RSTN_PIN ( BIT7 )
#define OLED_RSTN_CONFIG() { OLED_RSTN_PDIR |= OLED_RSTN_PIN; OLED_RSTN_ASSERT(); }
#define OLED_RSTN_ASSERT() { OLED_RSTN_POUT &= ~OLED_RSTN_PIN; }
#define OLED_RSTN_DEASSERT() { OLED_RSTN_POUT |= OLED_RSTN_PIN; }
#define OLED_CS1N_PDIR ( P8DIR )
#define OLED_CS1N_POUT ( P8OUT )
#define OLED_CS1N_PIN ( BIT0 )
#define OLED_CS1N_CONFIG() { OLED_CS1N_PDIR |= OLED_CS1N_PIN; OLED_CS1N_DISABLE(); }
#define OLED_CS1N_ENABLE() { OLED_CS1N_POUT &= ~OLED_CS1N_PIN; }
#define OLED_CS1N_DISABLE() { OLED_CS1N_POUT |= OLED_CS1N_PIN; }
#define OLED_CS2N_PDIR ( P8DIR )
#define OLED_CS2N_POUT ( P8OUT )
#define OLED_CS2N_PIN ( BIT1 )
#define OLED_CS2N_CONFIG() { OLED_CS2N_PDIR |= OLED_CS2N_PIN; OLED_CS2N_DISABLE(); }
#define OLED_CS2N_ENABLE() { OLED_CS2N_POUT &= ~OLED_CS2N_PIN; }
#define OLED_CS2N_DISABLE() { OLED_CS2N_POUT |= OLED_CS2N_PIN; }
#define OLED_SDA_PDIR ( P3DIR )
#define OLED_SDA_POUT ( P3OUT )
#define OLED_SDA_PIN ( BIT1 )
#define OLED_SDA_PSEL ( P3SEL)
#define OLED_SCL_PDIR ( P3DIR )
#define OLED_SCL_POUT ( P3OUT )
#define OLED_SCL_PORT ( P3 )
#define OLED_SCL_PIN ( BIT2 )
#define OLED_SCL_PSEL ( P3SEL )
// the select line overrides the pdir and pout settings
#define OLED_SDA_CONFIG_FOR_PERIPHERAL_USE() { OLED_SDA_PSEL |= OLED_SDA_PIN; }
#define OLED_SCL_CONFIG_FOR_PERIPHERAL_USE() { OLED_SCL_PSEL |= OLED_SCL_PIN; }
#define OLED_I2C_CONFIG_FOR_PERIPHERAL_USE() { \
OLED_SDA_CONFIG_FOR_PERIPHERAL_USE(); \
OLED_SCL_CONFIG_FOR_PERIPHERAL_USE(); }
#define OLED_SDA_CONFIG_FOR_SLEEP() { \
OLED_SDA_PSEL &= ~OLED_SDA_PIN; \
OLED_SDA_PDIR |= OLED_SDA_PIN; \
OLED_SDA_POUT |= OLED_SDA_PIN; }
#define OLED_SCL_CONFIG_FOR_SLEEP() { \
OLED_SCL_PSEL &= ~OLED_SCL_PIN; \
OLED_SCL_PDIR |= OLED_SCL_PIN; \
OLED_SCL_POUT |= OLED_SCL_PIN; }
#define OLED_I2C_CONFIG_FOR_SLEEP() { \
OLED_SDA_CONFIG_FOR_SLEEP(); \
OLED_SCL_CONFIG_FOR_SLEEP(); }
#define OLED_POWER_ENABLE_PIN ( BIT0 )
#define OLED_POWER_ENABLE_POUT ( P4OUT )
#define OLED_POWER_ENABLE_PDIR ( P4DIR )
#define OLED_POWER_CONFIG() { P4DIR |= OLED_POWER_ENABLE_PIN; OLED_POWER_DISABLE(); }
#define OLED_POWER_ENABLE() { P4OUT |= OLED_POWER_ENABLE_PIN; }
#define OLED_POWER_DISABLE() { P4OUT &= ~OLED_POWER_ENABLE_PIN; }
// VLED_EN is active low
#define OLED_IO_POWER_ENABLE_PIN ( BIT3 )
#define OLED_IO_POWER_ENABLE_POUT ( P5OUT )
#define OLED_IO_POWER_ENABLE_PDIR ( P5DIR )
#define OLED_IO_POWER_CONFIG() { P5DIR |= OLED_IO_POWER_ENABLE_PIN; OLED_IO_POWER_DISABLE(); }
#define OLED_IO_POWER_ENABLE() { P5OUT &= ~OLED_IO_POWER_ENABLE_PIN; }
#define OLED_IO_POWER_DISABLE() { P5OUT |= OLED_IO_POWER_ENABLE_PIN; }
#ifdef ANALOG
#define CONFIG_OLED_PINS() { \
OLED_RSTN_CONFIG(); \
OLED_CS1N_CONFIG(); \
OLED_CS2N_CONFIG(); \
OLED_POWER_CONFIG(); \
OLED_I2C_CONFIG_FOR_SLEEP(); \
OLED_IO_POWER_CONFIG(); \
}
#else
/* jumpers for 10V must be removed for power consumption measurements */
#define CONFIG_OLED_PINS() { \
OLED_RSTN_CONFIG(); \
OLED_CS1N_CONFIG(); \
OLED_CS1N_ENABLE(); \
OLED_CS2N_CONFIG(); \
OLED_CS2N_ENABLE(); \
OLED_POWER_CONFIG(); \
OLED_IO_POWER_CONFIG(); \
}
#endif
// Real time clock defines
// RTC 1 Hz output, also used to toggle the bias on the LCD
#define RTC_1HZ_PORT_DIR ( P2DIR )
#define RTC_1HZ_PORT_SEL ( P2SEL )
#define RTC_1HZ_BIT ( BIT4 )
// Button defines
#define BUTTON_TIME_COUNT_ARRAY_LEN 8
#define ALL_BUTTONS_OFF 0xFF
#define SW_A BIT0
#define SW_B BIT1
#define SW_C BIT2
#define SW_D BIT3
// Bit 4 is not used
#define SW_E BIT5
#define SW_F BIT6
#define SW_P BIT7
#define SW_A_INDEX ( 0 )
#define SW_B_INDEX ( 1 )
#define SW_C_INDEX ( 2 )
#define SW_D_INDEX ( 3 )
#define SW_UNUSED_INDEX ( 4 )
#define SW_E_INDEX ( 5 )
#define SW_F_INDEX ( 6 )
#define SW_P_INDEX ( 7 )
#define TOTAL_BTN_NUM ( 8 )
#ifdef ANALOG
/* analog board has traces for all of the buttons but
* only 3 and pull switch are populated */
#define ALL_BUTTONS (SW_A | SW_B | SW_C | SW_P)
#elif defined(DIGITAL)
#define ALL_BUTTONS (SW_A | SW_B | SW_C | SW_D | SW_E | SW_F)
#endif
#define RESISTOR_ENABLE_BUTTONS ( ALL_BUTTONS )
#define INT_EDGE_SEL_BUTTONS (ALL_BUTTONS)
#define BUTTON_PORT_VECTOR PORT2_VECTOR
#define BUTTON_PORT_DIR P2DIR
#define BUTTON_PORT_SEL P2SEL
#define BUTTON_PORT_OUT P2OUT
#define BUTTON_PORT_REN P2REN
#define BUTTON_PORT_IE P2IE
#define BUTTON_PORT_IES P2IES
#define BUTTON_PORT_IFG P2IFG
#define DISABLE_BUTTONS() { \
BUTTON_PORT_IE &= ~INT_EDGE_SEL_BUTTONS; \
BUTTON_PORT_REN &= ~ALL_BUTTONS; \
BUTTON_PORT_OUT &= ~ALL_BUTTONS; \
}
/* SHIPPING */
/* S5 or SW_E is the button that takes the watch out of shipping mode */
#define ENABLE_SHIPPING_WAKEUP() { \
P1IE = 0x00; \
PMMCTL0_H = 0xA5; \
PMMRIE = 0x0000; \
RTCPS0CTL = 0x0000; \
RTCPS1CTL = 0x0000; \
UCSCTL8 = 0x0700; \
BUTTON_PORT_REN = SW_E; \
BUTTON_PORT_OUT = SW_E; \
BUTTON_PORT_DIR &= ~SW_E; \
BUTTON_PORT_IES = SW_E; \
BUTTON_PORT_IFG = 0x00; \
BUTTON_PORT_IE = SW_E; \
}
// NOTE the the buttons are grounded. That means that we want to invert the bits
// when reading the port to have positive logic where a button press is a "1"
#define BUTTON_PORT_IN ~P2IN
// Configure the hardware port for the button support P2.4 is excluded
#define CONFIGURE_BUTTON_PINS() { \
BUTTON_PORT_REN = (unsigned char) RESISTOR_ENABLE_BUTTONS; \
BUTTON_PORT_OUT = (unsigned char) ALL_BUTTONS; \
BUTTON_PORT_DIR &= (unsigned char) ~ALL_BUTTONS; \
BUTTON_PORT_IES |= INT_EDGE_SEL_BUTTONS; \
BUTTON_PORT_IFG &= ~ALL_BUTTONS; \
BUTTON_PORT_IE |= ALL_BUTTONS; \
}
// Battery charger control for a BQ24080
#define BAT_CHARGE_DIR P6DIR
#define BAT_CHARGE_REN P6REN
#define BAT_CHARGE_OUT P6OUT
#define BAT_CHARGE_IN P6IN
//#define BAT_CHARGE_IE P6IE
//#define PWR_PORT_VECTOR PORT6_VECTOR
//#define PWR_PORT_IFG P6IFG
#define BAT_CHARGE_ENABLE_PIN BIT2
#define BAT_CHARGE_STAT1 BIT3
#define BAT_CHARGE_STAT2 BIT4
#define BAT_CHARGE_PWR_BIT BIT5
// Enable charging, asserted low
#define BATTERY_CHARGE_ENABLE() { BAT_CHARGE_OUT &= ~BAT_CHARGE_ENABLE_PIN; }
// disable charging, sleep the part
#define BATTERY_CHARGE_DISABLE() { BAT_CHARGE_OUT |= BAT_CHARGE_ENABLE_PIN; }
//RESET PIN NMI or RESET
#define SET_RESET_PIN_NMI() {SFRRPCR &= ~SYSRSTRE; SFRRPCR |= SYSNMI;}
#define SET_RESET_PIN_RST() {SFRRPCR |= SYSRSTRE; SFRRPCR &= ~SYSNMI;}
#define RESET_PIN (SFRRPCR & SYSNMI) // return 1 for NMI
//
// Ambient Light Sensor
//
#define GC1_PDIR ( P6DIR )
#define GC1_POUT ( P6OUT )
#define GC1_PSEL ( P6SEL )
#define GC1_PIN ( BIT0 )
#define GC2_PDIR ( P6DIR )
#define GC2_POUT ( P6OUT )
#define GC2_PSEL ( P6SEL )
#define GC2_PIN ( BIT6 )
#define IOUT_PDIR ( P6DIR )
#define IOUT_PSEL ( P6SEL )
#define IOUT_PIN ( BIT1 )
#define LIGHT_SENSE_INIT() \
{ \
IOUT_PDIR &= ~IOUT_PIN; \
IOUT_PSEL |= IOUT_PIN; \
GC1_PDIR |= GC1_PIN; \
GC2_PDIR |= GC2_PIN; \
LIGHT_SENSE_DISABLE(); \
}
#define LIGHT_SENSOR_SHUTDOWN() \
{ \
GC1_POUT &= ~GC1_PIN; \
GC2_POUT &= ~GC2_PIN; \
}
#define LIGHT_SENSOR_L_GAIN() \
{ \
GC1_POUT |= GC1_PIN; \
GC2_POUT |= GC2_PIN; \
}
#define LIGHT_SENSE_ENABLE()\
{ \
LIGHT_SENSOR_L_GAIN(); \
}
#define LIGHT_SENSE_DISABLE() \
{ \
LIGHT_SENSOR_SHUTDOWN(); \
}
//
// This pin controls if the battery voltage can be read
//
#define BATTERY_READ_CONTROL_PDIR ( P4DIR )
#define BATTERY_READ_CONTROL_POUT ( P4OUT )
#define BATTERY_READ_CONTROL_PIN ( BIT6 )
#define BATTERY_SENSE_INPUT_PDIR ( P7DIR )
#define BATTERY_SENSE_INPUT_PSEL ( P7SEL )
#define BATTERY_SENSE_INPUT_PIN ( BIT7 )
#define BATTERY_SENSE_INIT() \
{ \
BATTERY_READ_CONTROL_PDIR |= BATTERY_READ_CONTROL_PIN; \
BATTERY_SENSE_INPUT_PDIR &= ~BATTERY_SENSE_INPUT_PIN; \
BATTERY_SENSE_INPUT_PSEL |= BATTERY_SENSE_INPUT_PIN; \
BATTERY_SENSE_DISABLE(); \
}
#define BATTERY_SENSE_ENABLE() \
{ \
BATTERY_READ_CONTROL_POUT |= BATTERY_READ_CONTROL_PIN; \
}
#define BATTERY_SENSE_DISABLE() \
{ \
BATTERY_READ_CONTROL_POUT &= ~BATTERY_READ_CONTROL_PIN; \
}
//
// hardware configuration is a voltage divider to ADC input
//
#define HARDWARE_CFG_CONTROL_PDIR ( P5DIR )
#define HARDWARE_CFG_CONTROL_POUT ( P5OUT )
#define HARDWARE_CFG_CONTROL_PIN ( BIT0 )
#define HARDWARE_CFG_INPUT_PDIR ( P7DIR )
#define HARDWARE_CFG_INPUT_PSEL ( P7SEL )
#define HARDWARE_CFG_INPUT_PIN ( BIT5 )
#define HARDWARE_CFG_SENSE_INIT() \
{ \
HARDWARE_CFG_CONTROL_PDIR |= HARDWARE_CFG_CONTROL_PIN; \
HARDWARE_CFG_INPUT_PDIR &= ~HARDWARE_CFG_INPUT_PIN; \
HARDWARE_CFG_INPUT_PSEL |= HARDWARE_CFG_INPUT_PIN; \
HARDWARE_CFG_SENSE_DISABLE(); \
}
#define HARDWARE_CFG_SENSE_ENABLE() \
{ \
HARDWARE_CFG_CONTROL_POUT |= HARDWARE_CFG_CONTROL_PIN; \
}
#define HARDWARE_CFG_SENSE_DISABLE() \
{ \
HARDWARE_CFG_CONTROL_POUT &= ~HARDWARE_CFG_CONTROL_PIN; \
}
#define APPLE_SDA_PDIR ( P10DIR )
#define APPLE_SDA_POUT ( P10OUT )
#define APPLE_SDA_PIN ( BIT1 )
#define APPLE_SCL_PDIR ( P10DIR )
#define APPLE_SCL_POUT ( P10OUT )
#define APPLE_SCL_PIN ( BIT2 )
#define APPLE_POWER_PDIR ( P4DIR )
#define APPLE_POWER_POUT ( P4OUT )
#define APPLE_POWER_PIN ( BIT5 )
/* power enable is active low */
#define APPLE_POWER_ENABLE() { APPLE_POWER_POUT &= ~APPLE_POWER_PIN; }
#define APPLE_POWER_DISABLE() { APPLE_POWER_POUT |= APPLE_POWER_PIN; }
#define APPLE_POWER_CONFIG() { \
APPLE_POWER_PDIR |= APPLE_POWER_PIN; \
APPLE_POWER_DISABLE(); \
}
/* since the apple chip is currently not powered
* the pins should be at 0 instead of 1
*/
#define APPLE_I2C_PIN_CONFIG() { \
APPLE_SDA_PDIR |= APPLE_SDA_PIN; \
APPLE_SDA_POUT &= ~APPLE_SDA_PIN; \
APPLE_SCL_PDIR |= APPLE_SCL_PIN; \
APPLE_SCL_POUT &= ~APPLE_SCL_PIN; \
}
#define APPLE_CONFIG() { \
APPLE_POWER_CONFIG(); \
APPLE_I2C_PIN_CONFIG(); \
}
#define SRAM_SCLK_PSEL ( P3SEL )
#define SRAM_SCLK_PDIR ( P3DIR )
#define SRAM_SCLK_POUT ( P3OUT )
#define SRAM_SCLK_PIN ( BIT0 )
#define SRAM_SOMI_PSEL ( P3SEL )
#define SRAM_SOMI_PDIR ( P3DIR )
#define SRAM_SOMI_POUT ( P3OUT )
#define SRAM_SOMI_PIN ( BIT5 )
#define SRAM_SIMO_PSEL ( P3SEL )
#define SRAM_SIMO_PDIR ( P3DIR )
#define SRAM_SIMO_POUT ( P3OUT )
#define SRAM_SIMO_PIN ( BIT4 )
#define SRAM_CSN_PDIR ( P9DIR )
#define SRAM_CSN_POUT ( P9OUT )
#define SRAM_CSN_PIN ( BIT6)
#define SRAM_HOLDN_PDIR ( P9DIR )
#define SRAM_HOLDN_POUT ( P9OUT )
#define SRAM_HOLDN_PIN ( BIT7 )
#define CONFIG_SRAM_PINS() \
{ \
SRAM_CSN_PDIR |= SRAM_CSN_PIN; \
SRAM_CSN_POUT |= SRAM_CSN_PIN; \
SRAM_HOLDN_PDIR |= SRAM_HOLDN_PIN; \
SRAM_HOLDN_POUT |= SRAM_HOLDN_PIN; \
}
#define SRAM_CSN_ASSERT() { SRAM_CSN_POUT &= ~SRAM_CSN_PIN; }
#define SRAM_CSN_DEASSERT() { \
WAIT_FOR_SRAM_SPI_SHIFT_COMPLETE(); \
SRAM_CSN_POUT |= SRAM_CSN_PIN; \
}
/* wait for shift to complete ( ~3 us ) */
#define WAIT_FOR_SRAM_SPI_SHIFT_COMPLETE() { while( (UCA0STAT & 0x01) != 0 ); }
#define ACCELEROMETER_SDA_PIN ( BIT7 )
#define ACCELEROMETER_SDA_PSEL ( P3SEL )
#define ACCELEROMETER_SDA_POUT ( P3OUT )
#define ACCELEROMETER_SDA_PDIR ( P3OUT )
#define ACCELEROMETER_SDA_PREN ( P1REN )
#define ACCELEROMETER_SCL_PIN ( BIT4 )
#define ACCELEROMETER_SCL_PSEL ( P5SEL )
#define ACCELEROMETER_SCL_POUT ( P5OUT )
#define ACCELEROMETER_SCL_PDIR ( P5OUT )
#define ACCELEROMETER_SCL_PREN ( P5REN )
#define ACCELEROMETER_INT_PIN ( BIT7 )
#define ACCELEROMETER_INT_PDIR ( P1DIR )
#define ACCELEROMETER_INT_PSEL ( P1SEL )
#define ACCELEROMETER_INT_PIFG ( P1IFG )
#define ACCELEROMETER_INT_PIE ( P1IE )
#define ACCELEROMETER_POWER_POUT ( P9OUT )
#define ACCELEROMETER_POWER_PDIR ( P9DIR )
#define ACCELEROMETER_POWER_PINS ( BIT1 | BIT2 )
/* this is for reference only (it doesn't control anything) */
#define ACCELEROMETER_INT_NUM (PIN7_INT)
#define LED4_PIN ( BIT2 )
#define LED5_PIN ( BIT3 )
#define LED6_PIN ( BIT4 )
#define LED7_PIN ( BIT5 )
#define LEDS_PDIR ( P8DIR )
#define LEDS_POUT ( P8OUT )
#define LED4_ON() { LEDS_POUT |= LED4_PIN; }
#define LED5_ON() { LEDS_POUT |= LED5_PIN; }
#define LED6_ON() { LEDS_POUT |= LED6_PIN; }
#define LED7_ON() { LEDS_POUT |= LED7_PIN; }
#define LED4_OFF() { LEDS_POUT &= ~LED4_PIN; }
#define LED5_OFF() { LEDS_POUT &= ~LED5_PIN; }
#define LED6_OFF() { LEDS_POUT &= ~LED6_PIN; }
#define LED7_OFF() { LEDS_POUT &= ~LED7_PIN; }
#define LED4_TOGGLE() { LEDS_POUT ^= LED4_PIN; }
#define LED5_TOGGLE() { LEDS_POUT ^= LED5_PIN; }
#define LED6_TOGGLE() { LEDS_POUT ^= LED6_PIN; }
#define LED7_TOGGLE() { LEDS_POUT ^= LED7_PIN; }
#define CONFIG_LED_PINS() { \
LEDS_PDIR |= LED4_PIN | LED5_PIN | LED6_PIN | LED7_PIN; \
LED4_OFF(); LED5_OFF(); LED6_OFF(); LED7_OFF(); \
}
#define DEBUG1_PIN ( BIT1 )
#define DEBUG3_PIN ( BIT4 )
#define DEBUG4_PIN ( BIT7 )
#define DEBUG5_PIN ( BIT6 )
#define DEBUG1_PDIR ( P5DIR )
#define DEBUG3_PDIR ( P7DIR )
#define DEBUG4_PDIR ( P6DIR )
#define DEBUG5_PDIR ( P7DIR )
#define DEBUG1_POUT ( P5OUT )
#define DEBUG3_POUT ( P7OUT )
#define DEBUG4_POUT ( P6OUT )
#define DEBUG5_POUT ( P7OUT )
#define DEBUG1_HIGH() { DEBUG1_POUT |= DEBUG1_PIN; }
#define DEBUG3_HIGH() { DEBUG3_POUT |= DEBUG3_PIN; }
#define DEBUG4_HIGH() { DEBUG4_POUT |= DEBUG4_PIN; }
#define DEBUG5_HIGH() { DEBUG5_POUT |= DEBUG5_PIN; }
#define DEBUG1_LOW() { DEBUG1_POUT &= ~DEBUG1_PIN; }
#define DEBUG3_LOW() { DEBUG3_POUT &= ~DEBUG3_PIN; }
#define DEBUG4_LOW() { DEBUG4_POUT &= ~DEBUG4_PIN; }
#define DEBUG5_LOW() { DEBUG5_POUT &= ~DEBUG5_PIN; }
#define DEBUG1_PULSE() { DEBUG1_HIGH(); DEBUG1_LOW(); }
#define DEBUG3_PULSE() { DEBUG3_HIGH(); DEBUG3_LOW(); }
#define DEBUG4_PULSE() { DEBUG4_HIGH(); DEBUG4_LOW(); }
#define DEBUG5_PULSE() { DEBUG5_HIGH(); DEBUG5_LOW(); }
#define DEBUG1_TOGGLE() { DEBUG1_POUT ^= DEBUG1_PIN; }
#define DEBUG3_TOGGLE() { DEBUG3_POUT ^= DEBUG3_PIN; }
#define DEBUG4_TOGGLE() { DEBUG4_POUT ^= DEBUG4_PIN; }
#define DEBUG5_TOGGLE() { DEBUG5_POUT ^= DEBUG5_PIN; }
#define CONFIG_DEBUG_PINS() { \
DEBUG1_PDIR |= DEBUG1_PIN; \
DEBUG3_PDIR |= DEBUG3_PIN; \
DEBUG4_PDIR |= DEBUG4_PIN; \
DEBUG5_PDIR |= DEBUG5_PIN; \
DEBUG1_POUT &= ~DEBUG1_PIN; \
DEBUG3_POUT &= ~DEBUG3_PIN; \
DEBUG4_POUT &= ~DEBUG4_PIN; \
DEBUG5_POUT &= ~DEBUG5_PIN; \
}
/*
* Sideband signals (for lack of another word)
*/
#define BT_CLK_REQ_PDIR ( P1DIR )
#define BT_CLK_REQ_POUT ( P1OUT )
#define BT_CLK_REQ_PIN ( BIT4 )
#define BT_IO1_PDIR ( P1DIR )
#define BT_IO1_POUT ( P1OUT )
#define BT_IO1_PIN ( BIT5 )
#define BT_IO2_PDIR ( P1DIR )
#define BT_IO2_POUT ( P1OUT )
#define BT_IO2_PIN ( BIT6 )
/******************************************************************************/
/* peripheral mapping for accelerometer */
#define ACCELEROMETER_CTL0 ( UCB1CTL0 )
#define ACCELEROMETER_CTL1 ( UCB1CTL1 )
#define ACCELEROMETER_BR0 ( UCB1BR0 )
#define ACCELEROMETER_BR1 ( UCB1BR1 )
#define ACCELEROMETER_I2CSA ( UCB1I2CSA )
#define ACCELEROMETER_IE ( UCB1IE )
#define ACCELEROMETER_IFG ( UCB1IFG )
#define ACCELEROMETER_TXBUF ( UCB1TXBUF )
#define ACCELEROMETER_RXBUF ( UCB1RXBUF )
#define ACCELEROMETER_STAT ( UCB1STAT )
/* interrupt mapping for accelerometer */
#define USCI_ACCELEROMETER_VECTOR ( USCI_B1_VECTOR )
#define USCI_ACCELEROMETER_IV ( UCB1IV )
#endif // HAL_DEVBOARD_V2_DEFS_H

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@ -0,0 +1,619 @@
//==============================================================================
// Copyright 2011 Meta Watch Ltd. - http://www.MetaWatch.org/
//
// Licensed under the Meta Watch License, Version 1.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.MetaWatch.org/licenses/license-1.0.html
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//==============================================================================
/******************************************************************************/
/*! \file hal_digital_v2_defs.h
*
* Pin and peripheral definitions for Digital Watch Version 2
*/
/******************************************************************************/
#ifndef HAL_DIGITAL_V2_DEFS_H
#define HAL_DIGITAL_V2_DEFS_H
// Defines for the LCD display interface, single channel SPI output
#define LCD_5V_PDIR P4DIR
#define LCD_5V_POUT P4OUT
#define LCD_5V_BIT BIT0
#define ENABLE_LCD_POWER() { \
LCD_5V_PDIR |= LCD_5V_BIT; \
LCD_5V_POUT |= LCD_5V_BIT; \
}
#define DISABLE_LCD_POWER() { \
LCD_5V_PDIR |= LCD_5V_BIT; \
LCD_5V_POUT &= ~LCD_5V_BIT; \
}
#define LCD_ENABLE_PDIR ( P3DIR )
#define LCD_ENABLE_POUT ( P3OUT )
#define LCD_ENABLE_PIN ( BIT6 )
#define ENABLE_LCD_ENABLE() { \
LCD_ENABLE_PDIR |= LCD_ENABLE_PIN; \
LCD_ENABLE_POUT |= LCD_ENABLE_PIN; \
}
#define DISABLE_LCD_ENABLE() { \
LCD_ENABLE_PDIR |= LCD_ENABLE_PIN; \
LCD_ENABLE_POUT &= ~LCD_ENABLE_PIN; \
}
#define LCD_CS_PDIR ( P3DIR )
#define LCD_CS_POUT ( P3OUT )
#define LCD_CS_PIN ( BIT2 )
#define LCD_SPI_PORT_SEL ( P3SEL )
#define LCD_SPI_SIMO_BIT ( BIT1 )
#define LCD_SPI_CLK_BIT ( BIT3 )
#define LCD_CS_ASSERT() { LCD_CS_POUT |= LCD_CS_PIN; }
#define LCD_CS_DEASSERT() { LCD_CS_POUT &= ~LCD_CS_PIN; }
/* unused in this version */
#define SPECIAL_DMA_CONFIG() { }
#define OLED_CS1N_ENABLE() { }
#define OLED_CS1N_DISABLE() { }
#define CONFIG_LCD_PINS() { \
LCD_SPI_PORT_SEL |= LCD_SPI_SIMO_BIT; \
LCD_SPI_PORT_SEL |= LCD_SPI_CLK_BIT; \
ENABLE_LCD_ENABLE(); \
LCD_CS_PDIR |= LCD_CS_PIN; \
LCD_CS_DEASSERT(); \
}
// labeled EL_EN on schematic
#define LCD_LED_PDIR ( P4DIR )
#define LCD_LED_POUT ( P4OUT )
#define LCD_LED_PIN ( BIT4 )
#define DISABLE_LCD_LED() { \
LCD_LED_PDIR |= LCD_LED_PIN; \
LCD_LED_POUT &= ~LCD_LED_PIN; \
}
#define ENABLE_LCD_LED() { \
LCD_LED_PDIR |= LCD_LED_PIN; \
LCD_LED_POUT |= LCD_LED_PIN; \
}
// Use UCB2 as the SPI port define the registers and interrupt vector to all be
// for UCB2 by replacing the x in the last section of the name with a 2
#define LCD_SPI_UCBxCTL0 UCB0CTL0 // Control register
#define LCD_SPI_UCBxCTL1 UCB0CTL1 // Control register
#define LCD_SPI_UCBxBR0 UCB0BR0 // Baudrate prescale
#define LCD_SPI_UCBxBR1 UCB0BR1 // Baudrate divider
#define LCD_SPI_UCBxTXBUF UCB0TXBUF // Transmit buffer
#define LCD_SPI_UCBxRXBUF UCB0RXBUF // Receive buffer
#define LCD_SPI_UCBxIE UCB0IE // Interrupt enable register
#define LCD_SPI_UCBxIFG UCB0IFG // Interrupt flag register
#define LCD_SPI_UCBxIV UCB0IV // Interrupt vector register
#define LCD_SPI_UCBxSTAT UCB0STAT // status register
#if 0
// Definitions for the OLED Display
// peripheral mapping for OLED
#define OLED_I2C_CTL0 ( UCB0CTL0 )
#define OLED_I2C_CTL1 ( UCB0CTL1 )
#define OLED_I2C_BR0 ( UCB0BR0 )
#define OLED_I2C_BR1 ( UCB0BR1 )
#define OLED_I2C_I2CSA ( UCB0I2CSA )
#define OLED_I2C_IE ( UCB0IE )
#define OLED_I2C_IFG ( UCB0IFG )
#define OLED_I2C_TXBUF ( UCB0TXBUF )
#define OLED_I2C_RXBUF ( UCB0RXBUF )
// interrupt mapping for OLED
#define USCI_OLED_I2C_VECTOR ( USCI_B0_VECTOR )
#define USCI_OLED_I2C_IV ( UCB0IV )
// OLED reset is active low
#define OLED_RSTN_PDIR ( P3DIR )
#define OLED_RSTN_POUT ( P3OUT )
#define OLED_RSTN_PIN ( BIT3 )
#define OLED_RSTN_CONFIG() { OLED_RSTN_PDIR |= OLED_RSTN_PIN; OLED_RSTN_ASSERT(); }
#define OLED_RSTN_ASSERT() { OLED_RSTN_POUT &= ~OLED_RSTN_PIN; }
#define OLED_RSTN_DEASSERT() { OLED_RSTN_POUT |= OLED_RSTN_PIN; }
#define OLED_CS1N_PDIR ( P8DIR )
#define OLED_CS1N_POUT ( P8OUT )
#define OLED_CS1N_PIN ( BIT0 )
#define OLED_CS1N_CONFIG() { OLED_CS1N_PDIR |= OLED_CS1N_PIN; OLED_CS1N_DISABLE(); }
#define OLED_CS1N_ENABLE() { OLED_CS1N_POUT &= ~OLED_CS1N_PIN; }
#define OLED_CS1N_DISABLE() { OLED_CS1N_POUT |= OLED_CS1N_PIN; }
#define OLED_CS2N_PDIR ( P8DIR )
#define OLED_CS2N_POUT ( P8OUT )
#define OLED_CS2N_PIN ( BIT1 )
#define OLED_CS2N_CONFIG() { OLED_CS2N_PDIR |= OLED_CS2N_PIN; OLED_CS2N_DISABLE(); }
#define OLED_CS2N_ENABLE() { OLED_CS2N_POUT &= ~OLED_CS2N_PIN; }
#define OLED_CS2N_DISABLE() { OLED_CS2N_POUT |= OLED_CS2N_PIN; }
#define OLED_SDA_PDIR ( P3DIR )
#define OLED_SDA_POUT ( P3OUT )
#define OLED_SDA_PIN ( BIT1 )
#define OLED_SDA_PSEL ( P3SEL)
#define OLED_SCL_PDIR ( P3DIR )
#define OLED_SCL_POUT ( P3OUT )
#define OLED_SCL_PORT ( P3 )
#define OLED_SCL_PIN ( BIT2 )
#define OLED_SCL_PSEL ( P3SEL )
// the select line overrides the pdir and pout settings
#define OLED_SDA_CONFIG_FOR_PERIPHERAL_USE() { OLED_SDA_PSEL |= OLED_SDA_PIN; }
#define OLED_SCL_CONFIG_FOR_PERIPHERAL_USE() { OLED_SCL_PSEL |= OLED_SCL_PIN; }
#define OLED_I2C_CONFIG_FOR_PERIPHERAL_USE() { \
OLED_SDA_CONFIG_FOR_PERIPHERAL_USE(); \
OLED_SCL_CONFIG_FOR_PERIPHERAL_USE(); }
#define OLED_SDA_CONFIG_FOR_SLEEP() { \
OLED_SDA_PSEL &= ~OLED_SDA_PIN; \
OLED_SDA_PDIR |= OLED_SDA_PIN; \
OLED_SDA_POUT |= OLED_SDA_PIN; }
#define OLED_SCL_CONFIG_FOR_SLEEP() { \
OLED_SCL_PSEL &= ~OLED_SCL_PIN; \
OLED_SCL_PDIR |= OLED_SCL_PIN; \
OLED_SCL_POUT |= OLED_SCL_PIN; }
#define OLED_I2C_CONFIG_FOR_SLEEP() { \
OLED_SDA_CONFIG_FOR_SLEEP(); \
OLED_SCL_CONFIG_FOR_SLEEP(); }
#define OLED_POWER_ENABLE_PIN ( BIT0 )
#define OLED_POWER_ENABLE_POUT ( P4OUT )
#define OLED_POWER_ENABLE_PDIR ( P4DIR )
#define OLED_POWER_CONFIG() { P4DIR |= OLED_POWER_ENABLE_PIN; OLED_POWER_DISABLE(); }
#define OLED_POWER_ENABLE() { P4OUT |= OLED_POWER_ENABLE_PIN; }
#define OLED_POWER_DISABLE() { P4OUT &= ~OLED_POWER_ENABLE_PIN; }
// VLED_EN is active low
#define OLED_IO_POWER_ENABLE_PIN ( BIT3 )
#define OLED_IO_POWER_ENABLE_POUT ( P5OUT )
#define OLED_IO_POWER_ENABLE_PDIR ( P5DIR )
#define OLED_IO_POWER_CONFIG() { P5DIR |= OLED_IO_POWER_ENABLE_PIN; OLED_IO_POWER_DISABLE(); }
#define OLED_IO_POWER_ENABLE() { P5OUT &= ~OLED_IO_POWER_ENABLE_PIN; }
#define OLED_IO_POWER_DISABLE() { P5OUT |= OLED_IO_POWER_ENABLE_PIN; }
#endif // OLED
#define CONFIG_OLED_PINS() { }
// Real time clock defines
// RTC 1 Hz output, also used to toggle the bias on the LCD
#define RTC_1HZ_PORT_DIR ( P2DIR )
#define RTC_1HZ_PORT_SEL ( P2SEL )
#define RTC_1HZ_BIT ( BIT4 )
// Button defines
#define BUTTON_TIME_COUNT_ARRAY_LEN 8
#define ALL_BUTTONS_OFF 0xFF
#define SW_A BIT0
#define SW_B BIT1
#define SW_C BIT2
#define SW_D BIT3
// Bit 4 is not used
#define SW_E BIT5
#define SW_F BIT6
#define SW_P BIT7
#define SW_A_INDEX ( 0 )
#define SW_B_INDEX ( 1 )
#define SW_C_INDEX ( 2 )
#define SW_D_INDEX ( 3 )
#define SW_UNUSED_INDEX ( 4 )
#define SW_E_INDEX ( 5 )
#define SW_F_INDEX ( 6 )
#define SW_P_INDEX ( 7 )
/* the switch does not count */
#define TOTAL_BTN_NUM ( 7 )
#ifdef ANALOG
#define ALL_BUTTONS (SW_A | SW_B | SW_C | SW_D | SW_E | SW_F | SW_P)
#elif defined(DIGITAL)
#define ALL_BUTTONS (SW_A | SW_B | SW_C | SW_D | SW_E | SW_F)
#endif
// The digital watch version 1 has 1 Meg pull downs
// so the code below wont work
#define RESISTOR_ENABLE_BUTTONS ALL_BUTTONS
// Setting the edge select bit high generates and interrupt on the falling edge
#define INT_EDGE_SEL_BUTTONS (ALL_BUTTONS)
#define BUTTON_PORT_VECTOR PORT2_VECTOR
#define BUTTON_PORT_DIR P2DIR
#define BUTTON_PORT_SEL P2SEL
#define BUTTON_PORT_OUT P2OUT
#define BUTTON_PORT_REN P2REN
#define BUTTON_PORT_IE P2IE
#define BUTTON_PORT_IES P2IES
#define BUTTON_PORT_IFG P2IFG
#define DISABLE_BUTTONS() { \
BUTTON_PORT_IE &= ~INT_EDGE_SEL_BUTTONS; \
BUTTON_PORT_REN &= ~ALL_BUTTONS; \
BUTTON_PORT_OUT &= ~ALL_BUTTONS; \
}
/* SHIPPING */
/* S5 or SW_E is the button that takes the watch out of shipping mode */
#define ENABLE_SHIPPING_WAKEUP() { \
P1IE = 0x00; \
PMMCTL0_H = 0xA5; \
PMMRIE = 0x0000; \
RTCPS0CTL = 0x0000; \
RTCPS1CTL = 0x0000; \
UCSCTL8 = 0x0700; \
BUTTON_PORT_REN = SW_E; \
BUTTON_PORT_OUT = SW_E; \
BUTTON_PORT_DIR &= ~SW_E; \
BUTTON_PORT_IES |= SW_E; \
BUTTON_PORT_IFG = 0x00; \
BUTTON_PORT_IE |= SW_E; \
}
// NOTE the the buttons are grounded. That means that we want to invert the bits
// when reading the port to have positive logic where a button press is a "1"
#define BUTTON_PORT_IN ~P2IN
// Configure the hardware port for the button support P2.4 is excluded
#define CONFIGURE_BUTTON_PINS() { \
BUTTON_PORT_REN = (unsigned char) RESISTOR_ENABLE_BUTTONS; \
BUTTON_PORT_OUT = (unsigned char) ALL_BUTTONS; \
BUTTON_PORT_DIR &= (unsigned char) ~ALL_BUTTONS; \
BUTTON_PORT_IES |= INT_EDGE_SEL_BUTTONS; \
BUTTON_PORT_IFG &= ~ALL_BUTTONS; \
BUTTON_PORT_IE |= ALL_BUTTONS; \
}
// Battery charger control for a BQ24080
#define BAT_CHARGE_DIR P6DIR
#define BAT_CHARGE_REN P6REN
#define BAT_CHARGE_OUT P6OUT
#define BAT_CHARGE_IN P6IN
#define BAT_CHARGE_ENABLE_PIN BIT2
#define BAT_CHARGE_STAT1 BIT3
#define BAT_CHARGE_STAT2 BIT4
#define BAT_CHARGE_PWR_BIT BIT5
// Enable charging, asserted low
#define BATTERY_CHARGE_ENABLE() { BAT_CHARGE_OUT &= ~BAT_CHARGE_ENABLE_PIN; }
// disable charging, sleep the part
#define BATTERY_CHARGE_DISABLE() { BAT_CHARGE_OUT |= BAT_CHARGE_ENABLE_PIN; }
//RESET PIN NMI or RESET
#define SET_RESET_PIN_NMI() {SFRRPCR &= ~SYSRSTRE; SFRRPCR |= SYSNMI;}
#define SET_RESET_PIN_RST() {SFRRPCR |= SYSRSTRE; SFRRPCR &= ~SYSNMI;}
#define RESET_PIN (SFRRPCR & SYSNMI) // return 1 for NMI
//
// Ambient Light Sensor
//
#define GC1_PDIR ( P6DIR )
#define GC1_POUT ( P6OUT )
#define GC1_PSEL ( P6SEL )
#define GC1_PIN ( BIT0 )
#define GC2_PDIR ( P6DIR )
#define GC2_POUT ( P6OUT )
#define GC2_PSEL ( P6SEL )
#define GC2_PIN ( BIT6 )
#define IOUT_PDIR ( P6DIR )
#define IOUT_PSEL ( P6SEL )
#define IOUT_PIN ( BIT1 )
#define LIGHT_SENSE_INIT() \
{ \
IOUT_PDIR &= ~IOUT_PIN; \
IOUT_PSEL |= IOUT_PIN; \
GC1_PDIR |= GC1_PIN; \
GC2_PDIR |= GC2_PIN; \
LIGHT_SENSE_DISABLE(); \
}
#define LIGHT_SENSOR_SHUTDOWN() \
{ \
GC1_POUT &= ~GC1_PIN; \
GC2_POUT &= ~GC2_PIN; \
}
#define LIGHT_SENSOR_L_GAIN() \
{ \
GC1_POUT |= GC1_PIN; \
GC2_POUT |= GC2_PIN; \
}
#define LIGHT_SENSE_ENABLE()\
{ \
LIGHT_SENSOR_L_GAIN(); \
}
#define LIGHT_SENSE_DISABLE() \
{ \
LIGHT_SENSOR_SHUTDOWN(); \
}
//
// This pin controls if the battery voltage can be read
//
#define BATTERY_READ_CONTROL_PDIR ( P4DIR )
#define BATTERY_READ_CONTROL_POUT ( P4OUT )
#define BATTERY_READ_CONTROL_PIN ( BIT6 )
#define BATTERY_SENSE_INPUT_PDIR ( P7DIR )
#define BATTERY_SENSE_INPUT_PSEL ( P7SEL )
#define BATTERY_SENSE_INPUT_PIN ( BIT7 )
#define BATTERY_SENSE_INIT() \
{ \
BATTERY_READ_CONTROL_PDIR |= BATTERY_READ_CONTROL_PIN; \
BATTERY_SENSE_INPUT_PDIR &= ~BATTERY_SENSE_INPUT_PIN; \
BATTERY_SENSE_INPUT_PSEL |= BATTERY_SENSE_INPUT_PIN; \
BATTERY_SENSE_DISABLE(); \
}
#define BATTERY_SENSE_ENABLE() \
{ \
BATTERY_READ_CONTROL_POUT |= BATTERY_READ_CONTROL_PIN; \
}
#define BATTERY_SENSE_DISABLE() \
{ \
BATTERY_READ_CONTROL_POUT &= ~BATTERY_READ_CONTROL_PIN; \
}
//
// hardware configuration is a voltage divider to ADC input
//
#define HARDWARE_CFG_CONTROL_PDIR ( P8DIR )
#define HARDWARE_CFG_CONTROL_POUT ( P8OUT )
#define HARDWARE_CFG_CONTROL_PIN ( BIT2 )
#define HARDWARE_CFG_INPUT_PDIR ( P7DIR )
#define HARDWARE_CFG_INPUT_PSEL ( P7SEL )
#define HARDWARE_CFG_INPUT_PIN ( BIT5 )
#define HARDWARE_CFG_SENSE_INIT() \
{ \
HARDWARE_CFG_CONTROL_PDIR |= HARDWARE_CFG_CONTROL_PIN; \
HARDWARE_CFG_INPUT_PDIR &= ~HARDWARE_CFG_INPUT_PIN; \
HARDWARE_CFG_INPUT_PSEL |= HARDWARE_CFG_INPUT_PIN; \
HARDWARE_CFG_SENSE_DISABLE(); \
}
#define HARDWARE_CFG_SENSE_ENABLE() \
{ \
HARDWARE_CFG_CONTROL_POUT |= HARDWARE_CFG_CONTROL_PIN; \
}
#define HARDWARE_CFG_SENSE_DISABLE() \
{ \
HARDWARE_CFG_CONTROL_POUT &= ~HARDWARE_CFG_CONTROL_PIN; \
}
#define APPLE_SDA_PDIR ( P10DIR )
#define APPLE_SDA_POUT ( P10OUT )
#define APPLE_SDA_PIN ( BIT1 )
#define APPLE_SCL_PDIR ( P10DIR )
#define APPLE_SCL_POUT ( P10OUT )
#define APPLE_SCL_PIN ( BIT2 )
#define APPLE_POWER_PDIR ( P4DIR )
#define APPLE_POWER_POUT ( P4OUT )
#define APPLE_POWER_PIN ( BIT5 )
/* power enable is active low */
#define APPLE_POWER_ENABLE() { APPLE_POWER_POUT &= ~APPLE_POWER_PIN; }
#define APPLE_POWER_DISABLE() { APPLE_POWER_POUT |= APPLE_POWER_PIN; }
#define APPLE_POWER_CONFIG() { \
APPLE_POWER_PDIR |= APPLE_POWER_PIN; \
APPLE_POWER_DISABLE(); \
}
/* since the apple chip is currently not powered
* the pins should be at 0 instead of 1
*/
#define APPLE_I2C_PIN_CONFIG() { \
APPLE_SDA_PDIR |= APPLE_SDA_PIN; \
APPLE_SDA_POUT &= ~APPLE_SDA_PIN; \
APPLE_SCL_PDIR |= APPLE_SCL_PIN; \
APPLE_SCL_POUT &= ~APPLE_SCL_PIN; \
}
#define APPLE_CONFIG() { \
APPLE_POWER_CONFIG(); \
APPLE_I2C_PIN_CONFIG(); \
}
#define SRAM_SCLK_PSEL ( P3SEL )
#define SRAM_SCLK_PDIR ( P3DIR )
#define SRAM_SCLK_POUT ( P3OUT )
#define SRAM_SCLK_PIN ( BIT0 )
#define SRAM_SOMI_PSEL ( P3SEL )
#define SRAM_SOMI_PDIR ( P3DIR )
#define SRAM_SOMI_POUT ( P3OUT )
#define SRAM_SOMI_PIN ( BIT5 )
#define SRAM_SIMO_PSEL ( P3SEL )
#define SRAM_SIMO_PDIR ( P3DIR )
#define SRAM_SIMO_POUT ( P3OUT )
#define SRAM_SIMO_PIN ( BIT4 )
#define SRAM_CSN_PDIR ( P9DIR )
#define SRAM_CSN_POUT ( P9OUT )
#define SRAM_CSN_PIN ( BIT6)
#define SRAM_HOLDN_PDIR ( P9DIR )
#define SRAM_HOLDN_POUT ( P9OUT )
#define SRAM_HOLDN_PIN ( BIT7 )
#define CONFIG_SRAM_PINS() \
{ \
SRAM_CSN_PDIR |= SRAM_CSN_PIN; \
SRAM_CSN_POUT |= SRAM_CSN_PIN; \
SRAM_HOLDN_PDIR |= SRAM_HOLDN_PIN; \
SRAM_HOLDN_POUT |= SRAM_HOLDN_PIN; \
}
#define SRAM_CSN_ASSERT() { SRAM_CSN_POUT &= ~SRAM_CSN_PIN; }
#define SRAM_CSN_DEASSERT() { \
WAIT_FOR_SRAM_SPI_SHIFT_COMPLETE(); \
SRAM_CSN_POUT |= SRAM_CSN_PIN; \
}
/* wait for shift to complete ( ~3 us ) */
#define WAIT_FOR_SRAM_SPI_SHIFT_COMPLETE() { while( (UCA0STAT & 0x01) != 0 ); }
#define ACCELEROMETER_SDA_PIN ( BIT7 )
#define ACCELEROMETER_SDA_PSEL ( P3SEL )
#define ACCELEROMETER_SDA_POUT ( P3OUT )
#define ACCELEROMETER_SDA_PDIR ( P3OUT )
#define ACCELEROMETER_SDA_PREN ( P1REN )
#define ACCELEROMETER_SCL_PIN ( BIT4 )
#define ACCELEROMETER_SCL_PSEL ( P5SEL )
#define ACCELEROMETER_SCL_POUT ( P5OUT )
#define ACCELEROMETER_SCL_PDIR ( P5OUT )
#define ACCELEROMETER_SCL_PREN ( P5REN )
#define ACCELEROMETER_INT_PIN ( BIT7 )
#define ACCELEROMETER_INT_PDIR ( P1DIR )
#define ACCELEROMETER_INT_PSEL ( P1SEL )
#define ACCELEROMETER_INT_PIFG ( P1IFG )
#define ACCELEROMETER_INT_PIE ( P1IE )
#define ACCELEROMETER_POWER_POUT ( P9OUT )
#define ACCELEROMETER_POWER_PDIR ( P9DIR )
#define ACCELEROMETER_POWER_PINS ( BIT1 | BIT2 )
/* this is for reference only (it doesn't control anything) */
#define ACCELEROMETER_INT_NUM (PIN7_INT)
#define LED4_ON() { }
#define LED5_ON() { }
#define LED6_ON() { }
#define LED7_ON() { }
#define LED4_OFF() { }
#define LED5_OFF() { }
#define LED6_OFF() { }
#define LED7_OFF() { }
#define CONFIG_LED_PINS() { }
#define DEBUG1_HIGH() { }
#define DEBUG3_HIGH() { }
#define DEBUG4_HIGH() { }
#define DEBUG5_HIGH() { }
#define DEBUG1_LOW() { }
#define DEBUG3_LOW() { }
#define DEBUG4_LOW() { }
#define DEBUG5_LOW() { }
#define DEBUG1_PULSE() { }
#define DEBUG3_PULSE() { }
#define DEBUG4_PULSE() { }
#define DEBUG5_PULSE() { }
#define DEBUG1_TOGGLE() { }
#define DEBUG3_TOGGLE() { }
#define DEBUG4_TOGGLE() { }
#define DEBUG5_TOGGLE() { }
#define CONFIG_DEBUG_PINS() { }
/*
* Sideband signals (for lack of another word)
*/
#define BT_CLK_REQ_PDIR ( P1DIR )
#define BT_CLK_REQ_POUT ( P1OUT )
#define BT_CLK_REQ_PIN ( BIT4 )
#define BT_IO1_PDIR ( P1DIR )
#define BT_IO1_POUT ( P1OUT )
#define BT_IO1_PIN ( BIT5 )
#define BT_IO2_PDIR ( P1DIR )
#define BT_IO2_POUT ( P1OUT )
#define BT_IO2_PIN ( BIT6 )
/******************************************************************************/
/* peripheral mapping for accelerometer */
#define ACCELEROMETER_CTL0 ( UCB1CTL0 )
#define ACCELEROMETER_CTL1 ( UCB1CTL1 )
#define ACCELEROMETER_BR0 ( UCB1BR0 )
#define ACCELEROMETER_BR1 ( UCB1BR1 )
#define ACCELEROMETER_I2CSA ( UCB1I2CSA )
#define ACCELEROMETER_IE ( UCB1IE )
#define ACCELEROMETER_IFG ( UCB1IFG )
#define ACCELEROMETER_TXBUF ( UCB1TXBUF )
#define ACCELEROMETER_RXBUF ( UCB1RXBUF )
#define ACCELEROMETER_STAT ( UCB1STAT )
/* interrupt mapping for accelerometer */
#define USCI_ACCELEROMETER_VECTOR ( USCI_B1_VECTOR )
#define USCI_ACCELEROMETER_IV ( UCB1IV )
/******************************************************************************/
/* IN1 on mux */
#define MUX_CONTROL1_PDIR ( P10DIR )
#define MUX_CONTROL1_POUT ( P10OUT )
#define MUX_CONTROL1_PIN ( BIT7 )
#define MUX_CONTROL2_PDIR ( P10DIR )
#define MUX_CONTROL2_POUT ( P10OUT )
#define MUX_CONTROL2_PIN ( BIT6 )
#endif // HAL_DIGITAL_V2_DEFS_H

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//==============================================================================
// Copyright Meta Watch Ltd. - http://www.MetaWatch.org/
//
// Licensed under the Meta Watch License, Version 1.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.MetaWatch.org/licenses/license-1.0.html
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//==============================================================================
/******************************************************************************/
/*! \file hal_io_macros.c
*
* Separate the pin definitions for each board type from the macros
*
*/
/******************************************************************************/
#ifndef HAL_IO_MACROS
#define HAL_IO_MACROS
/******************************************************************************/
#define BT_CLK_REQ_CONFIG_AS_INPUT() { \
BT_CLK_REQ_PDIR &= ~BT_CLK_REQ_PIN; \
}
#define BT_CLK_REQ_CONFIG_AS_OUTPUT_LOW() { \
BT_CLK_REQ_PDIR |= BT_CLK_REQ_PIN; \
BT_CLK_REQ_POUT &= ~BT_CLK_REQ_PIN; \
}
#define BT_IO1_CONFIG_AS_INPUT() { \
BT_IO1_PDIR &= ~BT_IO1_PIN; }
#define BT_IO1_CONFIG_AS_OUTPUT_LOW() { \
BT_IO1_PDIR |= BT_IO1_PIN; \
BT_IO1_POUT &= ~BT_IO1_PIN; \
}
#define BT_IO2_CONFIG_AS_INPUT() { \
BT_IO2_PDIR &= ~BT_IO2_PIN; \
}
#define BT_IO2_CONFIG_AS_OUTPUT_LOW() { \
BT_IO2_PDIR |= BT_IO2_PIN; \
BT_IO2_POUT &= ~BT_IO2_PIN; }
/******************************************************************************/
#define ACCELEROMETER_INT_ENABLE() { \
ACCELEROMETER_INT_PIFG &= ~ACCELEROMETER_INT_PIN; \
ACCELEROMETER_INT_PIE |= ACCELEROMETER_INT_PIN; \
}
#define ACCELEROMETER_INT_DISABLE() { \
ACCELEROMETER_INT_PIE &= ~ACCELEROMETER_INT_PIN; \
ACCELEROMETER_INT_PIFG &= ~ACCELEROMETER_INT_PIN; \
}
#define CONFIG_ACCELEROMETER_PINS() { \
ACCELEROMETER_SDA_PSEL |= ACCELEROMETER_SDA_PIN; \
ACCELEROMETER_SCL_PSEL |= ACCELEROMETER_SCL_PIN; \
ACCELEROMETER_INT_PDIR &= ~ACCELEROMETER_INT_PIN; \
}
/* only configuration 5 and later boards support turning on/off the power
* to the accelerometer
*/
#define ENABLE_ACCELEROMETER_POWER() { \
ACCELEROMETER_POWER_PDIR |= ACCELEROMETER_POWER_PINS; \
ACCELEROMETER_POWER_POUT |= ACCELEROMETER_POWER_PINS; \
}
#define DISABLE_ACCELEROMETER_POWER() { \
ACCELEROMETER_POWER_PDIR |= ACCELEROMETER_POWER_PINS; \
ACCELEROMETER_POWER_POUT &= ~ACCELEROMETER_POWER_PINS; \
}
/******************************************************************************/
#define ENABLE_MUX_OUTPUT_CONTROL() { \
MUX_CONTROL1_PDIR |= MUX_CONTROL1_PIN; \
MUX_CONTROL2_PDIR |= MUX_CONTROL2_PIN; \
}
#define MUX_OUTPUT_OFF() { \
MUX_CONTROL1_POUT &= ~MUX_CONTROL1_PIN; \
MUX_CONTROL2_POUT &= ~MUX_CONTROL2_PIN; \
}
#define MUX_OUTPUT_SELECTS_SERIAL() { \
MUX_CONTROL1_POUT |= MUX_CONTROL1_PIN; \
MUX_CONTROL2_POUT &= ~MUX_CONTROL2_PIN; \
}
#define MUX_OUTPUT_SELECTS_GND() { \
MUX_CONTROL1_POUT &= ~MUX_CONTROL1_PIN; \
MUX_CONTROL2_POUT |= MUX_CONTROL2_PIN; \
}
#define MUX_OUTPUT_SELECTS_SPY() { \
MUX_CONTROL1_POUT |= MUX_CONTROL1_PIN; \
MUX_CONTROL2_POUT |= MUX_CONTROL2_PIN; \
}
/******************************************************************************/
#endif /* HAL_IO_MACROS */

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#include <msp430.h>
#include <msp430xgeneric.h>
#include <stdint.h>
#include <stdio.h>
#include "mw_main.h"
#include "mw_uart.h"
#include "mw_acc.h"
#include "oswald_main.h"
#define ACCEL_STATE_DISABLED 0x00
#define ACCEL_STATE_ENABLED 0x01
static uint8_t AccelState;
static uint8_t AccelerometerBusy;
static uint8_t LengthCount;
static uint8_t Index;
static uint8_t *pAccelerometerData;
/*
* Accelerometer is a Kionix KXTF9-4100 connected to I2C
* I2C is pretty slow so reading and writing should be done non blocking
* using interrupts.
*/
#define ACCELEROMETER_NO_INTERRUPTS 0x00
#define ACCELEROMETER_ALIFG 0x02
#define ACCELEROMETER_NACKIFG 0x04
#define ACCELEROMETER_STTIFG 0x06
#define ACCELEROMETER_STPIFG 0x08
#define ACCELEROMETER_RXIFG 0x0a
#define ACCELEROMETER_TXIFG 0x0c
#pragma vector=USCI_B1_VECTOR
__interrupt void ACCERLEROMETER_I2C_ISR(void)
{
// debug_uart_tx("ACC i2c irq\n");
switch (USCI_ACCELEROMETER_IV) {
case ACCELEROMETER_NO_INTERRUPTS:
break;
case ACCELEROMETER_ALIFG:
break;
case ACCELEROMETER_NACKIFG:
nop();
break;
case ACCELEROMETER_STTIFG:
nop();
break;
case ACCELEROMETER_STPIFG:
nop();
break;
case ACCELEROMETER_RXIFG:
if (LengthCount > 0) {
pAccelerometerData[Index++] = ACCELEROMETER_RXBUF;
LengthCount--;
if ( LengthCount == 1 ) {
/* All but one byte received. Send stop */
ACCELEROMETER_CTL1 |= UCTXSTP;
} else if ( LengthCount == 0 ) {
/* Last byte received; disable rx interrupt */
ACCELEROMETER_IE &= ~UCRXIE;
AccelerometerBusy = 0;
}
}
break;
case ACCELEROMETER_TXIFG:
if ( LengthCount > 0 ) {
ACCELEROMETER_TXBUF = pAccelerometerData[Index++];
LengthCount--;
} else {
/* disable transmit interrupt and send stop */
ACCELEROMETER_IE &= ~UCTXIE;
ACCELEROMETER_CTL1 |= UCTXSTP;
AccelerometerBusy = 0;
}
break;
default:
break;
}
}
void mw_acc_init_i2c(void)
{
/* enable reset before configuration */
ACCELEROMETER_CTL1 |= UCSWRST;
/* configure as master using smclk / 40 = 399.5 kHz */
ACCELEROMETER_CTL0 = UCMST + UCMODE_3 + UCSYNC;
ACCELEROMETER_CTL1 = UCSSEL__SMCLK + UCSWRST;
ACCELEROMETER_BR0 = 42;
ACCELEROMETER_BR1 = 0;
ACCELEROMETER_I2CSA = KIONIX_DEVICE_ADDRESS;
/* release reset */
ACCELEROMETER_CTL1 &= ~UCSWRST;
}
void mw_acc_disable_i2c(void)
{
/* enable reset to hold it */
ACCELEROMETER_CTL1 |= UCSWRST;
}
void mw_acc_i2c_write(uint8_t RegisterAddress, uint8_t *pData, uint8_t Length)
{
int tmo;
if (Length == 0 || pData == 0)
return;
while (UCB1STAT & UCBBUSY)
nop();
AccelerometerBusy = 1;
LengthCount = Length;
Index = 0;
pAccelerometerData = pData;
/*
* enable transmit interrupt and
* setup for write and send the start condition
*/
ACCELEROMETER_IFG = 0;
ACCELEROMETER_CTL1 |= UCTR + UCTXSTT;
while(!(ACCELEROMETER_IFG & UCTXIFG))
nop();
/*
* clear transmit interrupt flag, enable interrupt,
* send the register address
*/
ACCELEROMETER_IFG = 0;
ACCELEROMETER_IE |= UCTXIE;
ACCELEROMETER_TXBUF = RegisterAddress;
tmo = 0;
while (AccelerometerBusy) {
while (tmo++ < 1000)
__delay_cycles(16000);
if (tmo >= 1000) {
debug_uart_tx("ACC I2C tx tmo\n");
return;
}
}
while (ACCELEROMETER_CTL1 & UCTXSTP)
nop();
/* the rest of TX will be handled by the ISR */
}
void mw_acc_i2c_read_single(const uint8_t RegisterAddress, const uint8_t *pData)
{
if ( pData == 0 )
return;
/* wait for bus to be free */
while (UCB1STAT & UCBBUSY)
nop();
AccelerometerBusy = 1;
LengthCount = 1;
Index = 0;
pAccelerometerData = (uint8_t *)pData;
/* transmit address */
ACCELEROMETER_IFG = 0;
ACCELEROMETER_CTL1 |= UCTR + UCTXSTT;
while (!(ACCELEROMETER_IFG & UCTXIFG))
nop();
/* write register address */
ACCELEROMETER_IFG = 0;
ACCELEROMETER_TXBUF = RegisterAddress;
while (!(ACCELEROMETER_IFG & UCTXIFG))
nop();
/* send a repeated start (same slave address now it is a read command)
* read possible extra character from rxbuffer
*/
ACCELEROMETER_RXBUF;
ACCELEROMETER_IFG = 0;
ACCELEROMETER_IE |= UCRXIE;
ACCELEROMETER_CTL1 &= ~UCTR;
/* for a read of a single byte the stop must be sent while the byte is being
* received. If this is interrupted an extra byte may be read.
* however, it will be discarded during the next read
*/
if (LengthCount == 1) {
/* errata usci30: prevent interruption of sending stop
* so that only one byte is read
* this requires 62 us @ 320 kHz, 51 @ 400 kHz
*/
__disable_interrupt();
ACCELEROMETER_CTL1 |= UCTXSTT;
while(ACCELEROMETER_CTL1 & UCTXSTT)
nop();
ACCELEROMETER_CTL1 |= UCTXSTP;
__enable_interrupt();
} else {
ACCELEROMETER_CTL1 |= UCTXSTT;
}
/* wait until all data has been received and the stop bit has been sent */
while (AccelerometerBusy)
nop();
while (ACCELEROMETER_CTL1 & UCTXSTP)
nop();
Index = 0;
pAccelerometerData = 0;
}
/* errata usci30: only perform single reads
* second solution: use DMA
*/
void mw_acc_i2c_read(const uint8_t RegisterAddress, uint8_t *pData, const uint8_t Length)
{
int i;
for ( i = 0; i < Length; i++ ) {
mw_acc_i2c_read_single(RegisterAddress + i, (pData + i));
}
}
void mw_acc_init(void)
{
uint8_t WriteRegisterData;
uint8_t pReadRegisterData[4];
#if defined MW_DEVBOARD_V2
char tstr[16];
#endif
// it takes at least 20ms to power up
ENABLE_ACCELEROMETER_POWER();
__delay_cycles(320000);
mw_acc_init_i2c();
/*
* make sure part is in standby mode because some registers can only
* be changed when the part is not active.
*/
WriteRegisterData = PC1_STANDBY_MODE;
mw_acc_i2c_write(KIONIX_CTRL_REG1, &WriteRegisterData, 1);
/* enable face-up and face-down detection */
WriteRegisterData = TILT_FDM | TILT_FUM;
mw_acc_i2c_write(KIONIX_CTRL_REG2, &WriteRegisterData, 1);
/*
* the interrupt from the accelerometer can be used to get periodic data
* the real time clock can also be used
*/
/* change to output data rate to 25 Hz */
WriteRegisterData = WUF_ODR_25HZ | TAP_ODR_400HZ;
mw_acc_i2c_write(KIONIX_CTRL_REG3, &WriteRegisterData, 1);
/* enable interrupt and make it active high */
WriteRegisterData = IEN | IEA;
mw_acc_i2c_write(KIONIX_INT_CTRL_REG1, &WriteRegisterData, 1);
/* enable motion detection interrupt for all three axis */
WriteRegisterData = XBW | YBW | ZBW;
mw_acc_i2c_write(KIONIX_INT_CTRL_REG2, &WriteRegisterData, 1);
/* enable tap interrupt for Z-axis */
WriteRegisterData = TFDM;
mw_acc_i2c_write(KIONIX_INT_CTRL_REG3, &WriteRegisterData, 1);
/* set TDT_TIMER to 0.2 secs*/
WriteRegisterData = 0x50;
mw_acc_i2c_write(KIONIX_TDT_TIMER, &WriteRegisterData, 1);
/* set tap low and high thresholds (default: 26 and 182) */
WriteRegisterData = 40; //78;
mw_acc_i2c_write(KIONIX_TDT_L_THRESH, &WriteRegisterData, 1);
WriteRegisterData = 128;
mw_acc_i2c_write(KIONIX_TDT_H_THRESH, &WriteRegisterData, 1);
/* set WUF_TIMER counter */
WriteRegisterData = 10;
mw_acc_i2c_write(KIONIX_WUF_TIMER, &WriteRegisterData, 1);
/* this causes data to always be sent */
// WriteRegisterData = 0x00;
WriteRegisterData = 0x01 /*0x08*/;
mw_acc_i2c_write(KIONIX_WUF_THRESH, &WriteRegisterData, 1);
/* single byte read test */
mw_acc_i2c_read(KIONIX_DCST_RESP, pReadRegisterData, 1);
#if defined MW_DEVBOARD_V2
snprintf(tstr, 16, "acc DCST 0x%02x\n", pReadRegisterData[0]);
debug_uart_tx(tstr);
#endif
/* multiple byte read test */
mw_acc_i2c_read(KIONIX_WHO_AM_I, pReadRegisterData, 2);
#if defined MW_DEVBOARD_V2
snprintf(tstr, 16, "acc is 0x%02x 0x%02x\n", pReadRegisterData[0], pReadRegisterData[1]);
debug_uart_tx(tstr);
#endif
/*
* KIONIX_CTRL_REG3 and DATA_CTRL_REG can remain at their default values
*
* 50 Hz
*/
#if 0
/* KTXF9 300 uA; KTXI9 165 uA */
WriteRegisterData = PC1_OPERATING_MODE | TAP_ENABLE_TDTE;
/* 180 uA; KTXI9 115 uA */
WriteRegisterData = PC1_OPERATING_MODE | RESOLUTION_8BIT | WUF_ENABLE;
/* 180 uA; KTXI9 8.7 uA */
WriteRegisterData = PC1_OPERATING_MODE | TILT_ENABLE_TPE;
/* 720 uA; KTXI9 330 uA */
WriteRegisterData = PC1_OPERATING_MODE | RESOLUTION_12BIT | WUF_ENABLE;
#endif
/* setup the default for the AccelerometerEnable command */
#if 0
OperatingModeRegister = PC1_OPERATING_MODE | RESOLUTION_12BIT | TAP_ENABLE_TDTE | TILT_ENABLE_TPE; // | WUF_ENABLE;
InterruptControl = INTERRUPT_CONTROL_DISABLE_INTERRUPT;
SidControl = SID_CONTROL_SEND_DATA;
SidAddr = KIONIX_XOUT_L;
SidLength = XYZ_DATA_LENGTH;
AccelState = ACCEL_STATE_INIT;
#endif
}
void mw_acc_enable(void)
{
uint8_t sdata;
mw_acc_init();
sdata = PC1_OPERATING_MODE | RESOLUTION_12BIT | TAP_ENABLE_TDTE | TILT_ENABLE_TPE | WUF_ENABLE;
//sdata = PC1_OPERATING_MODE | RESOLUTION_8BIT | TAP_ENABLE_TDTE | TILT_ENABLE_TPE; // | WUF_ENABLE;
mw_acc_i2c_write(KIONIX_CTRL_REG1, &sdata, 1);
ACCELEROMETER_INT_ENABLE();
mw_acc_i2c_read(KIONIX_INT_REL, &sdata, 1);
AccelState = ACCEL_STATE_ENABLED;
}
void mw_acc_disable(void)
{
uint8_t sdata;
if (AccelState == ACCEL_STATE_ENABLED) {
sdata = PC1_STANDBY_MODE;
mw_acc_i2c_write(KIONIX_CTRL_REG1, &sdata, 1);
ACCELEROMETER_INT_DISABLE();
mw_acc_disable_i2c();
/// DISABLE_ACCELEROMETER_POWER();
AccelState = ACCEL_STATE_DISABLED;
}
}
void mw_acc_read(int16_t *x, int16_t *y, int16_t *z)
{
uint8_t rdata[6];
if (AccelState == ACCEL_STATE_ENABLED) {
mw_acc_i2c_read(KIONIX_XOUT_L, rdata, 6);
*x = rdata[0] | (rdata[1] << 8);
*y = rdata[2] | (rdata[3] << 8);
*z = rdata[4] | (rdata[5] << 8);
} else {
*x = 0;
*y = 0;
*z = 0;
}
}
void mw_acc_handle_irq(void)
{
uint8_t sdata, srcreg1, srcreg2;
#if defined MW_DEVBOARD_V2
char tstr[16];
#endif
if (AccelState != ACCEL_STATE_ENABLED)
return;
mw_acc_i2c_read(KIONIX_INT_SRC_REG1, &srcreg1, 1);
#if defined MW_DEVBOARD_V2
snprintf(tstr, 16, "accsrc1: 0x%02x\n", srcreg1);
debug_uart_tx(tstr);
#endif
mw_acc_i2c_read(KIONIX_INT_SRC_REG2, &srcreg2, 1);
#if defined MW_DEVBOARD_V2
snprintf(tstr, 16, "accsrc2: 0x%02x\n", srcreg2);
debug_uart_tx(tstr);
#endif
if (srcreg1 & INT_TAP_SINGLE) {
};
if (srcreg1 & INT_TAP_DOUBLE) {
};
if (srcreg2 & INT_WUFS) {
int16_t x, y, z;
mw_acc_read(&x, &y, &z);
oswald_handle_accel_event((int8_t)(x / (32768 / 255)), (int8_t)(y / (32768 / 255)), (int8_t)(z / (32768 / 255)));
}
mw_acc_i2c_read(KIONIX_INT_REL, &sdata, 1);
}

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#ifndef _MW_ACC_H
#define _MW_ACC_H
#define KIONIX_DEVICE_ADDRESS ( 0x0F )
/* KIONIX accelerometer register addresses */
#define KIONIX_XOUT_HPF_L ( 0x00 )
#define KIONIX_XOUT_HPF_H ( 0x01 )
#define KIONIX_YOUT_HPF_L ( 0x02 )
#define KIONIX_YOUT_HPF_H ( 0x03 )
#define KIONIX_ZOUT_HPF_L ( 0x04 )
#define KIONIX_ZOUT_HPF_H ( 0x05 )
#define KIONIX_XOUT_L ( 0x06 )
#define KIONIX_XOUT_H ( 0x07 )
#define KIONIX_YOUT_L ( 0x08 )
#define KIONIX_YOUT_H ( 0x09 )
#define KIONIX_ZOUT_L ( 0x0A )
#define KIONIX_ZOUT_H ( 0x0B )
#define KIONIX_DCST_RESP ( 0x0C )
#define KIONIX_WHO_AM_I ( 0x0F )
#define KIONIX_TILT_POS_CUR ( 0x10 )
#define KIONIX_TILT_POS_PRE ( 0x11 )
#define KIONIX_INT_SRC_REG1 ( 0x15 )
#define KIONIX_INT_SRC_REG2 ( 0x16 )
#define KIONIX_STATUS_REG ( 0x18 )
#define KIONIX_INT_REL ( 0x1A )
#define KIONIX_CTRL_REG1 ( 0x1B )
#define KIONIX_CTRL_REG2 ( 0x1C )
#define KIONIX_CTRL_REG3 ( 0x1D )
#define KIONIX_INT_CTRL_REG1 ( 0x1E )
#define KIONIX_INT_CTRL_REG2 ( 0x1F )
#define KIONIX_INT_CTRL_REG3 ( 0x20 )
#define KIONIX_DATA_CTRL_REG ( 0x21 )
#define KIONIX_TILT_TIMER ( 0x28 )
#define KIONIX_WUF_TIMER ( 0x29 )
#define KIONIX_TDT_TIMER ( 0x2B )
#define KIONIX_TDT_H_THRESH ( 0x2C )
#define KIONIX_TDT_L_THRESH ( 0x2D )
#define KIONIX_TDT_TAP_TIMER ( 0x2E )
#define KIONIX_TDT_TOTAL_TIMER ( 0x2F )
#define KIONIX_TDT_LATENCY_TIMER ( 0x30 )
#define KIONIX_TDT_WINDOW_TIMER ( 0x31 )
#define KIONIX_SELF_TEST ( 0x3A )
#define KIONIX_WUF_THRESH ( 0x5A )
#define KIONIX_TILT_ANGLE ( 0x5C )
#define KIONIX_HYST_SET ( 0x5F )
/* CTRL_REG1 */
#define PC1_STANDBY_MODE ( 0 << 7 )
#define PC1_OPERATING_MODE ( 1 << 7 )
#define RESOLUTION_8BIT ( 0 << 6 )
#define RESOLUTION_12BIT ( 1 << 6 )
#define DRDYE_DATA_AVAILABLE ( 1 << 5 )
#define WUF_ENABLE ( 1 << 1 )
#define TAP_ENABLE_TDTE ( 1 << 2 )
#define TILT_ENABLE_TPE ( 1 << 0 )
/* CTRL_REG2 */
#define TILT_LEM (1 << 5 )
#define TILT_RIM (1 << 4 )
#define TILT_DOM (1 << 3 )
#define TILT_UPM (1 << 2 )
#define TILT_FDM (1 << 1 )
#define TILT_FUM (1 << 0 )
/* CTRL_REG3 */
#define SRST ( 1 << 7 )
#define TILT_ODR_1_6HZ ( 0 << 5 )
#define TILT_ODR_6_3HZ ( 1 << 5 )
#define TILT_ODR_12_5HZ ( 2 << 5 )
#define TILT_ODR_50HZ ( 3 << 5 )
#define DCST ( 1 << 4 )
#define TAP_ODR_50HZ ( 0 << 2 )
#define TAP_ODR_100HZ ( 1 << 2 )
#define TAP_ODR_200HZ ( 2 << 2 )
#define TAP_ODR_400HZ ( 3 << 2 )
#define WUF_ODR_25HZ ( 0 << 0 )
#define WUF_ODR_50HZ ( 1 << 0 )
#define WUF_ODR_100HZ ( 2 << 0 )
#define WUF_ODR_200HZ ( 3 << 0 )
/* INT_CTRL_REG1 */
#define IEN ( 1 << 5 )
#define IEA ( 1 << 4 )
#define IEL ( 1 << 3 )
#define IEU ( 1 << 2 )
/* INT_CTRL_REG2 */
#define XBW ( 1 << 7 )
#define YBW ( 1 << 6 )
#define ZBW ( 1 << 5 )
/* INT_CTRL_REG3 */
#define TLEM (1 << 5)
#define TRIM (1 << 4)
#define TDOM (1 << 3)
#define TUPM (1 << 2)
#define TFDM (1 << 1)
#define TFUM (1 << 0)
/* INT_SRC_REG2 */
#define INT_TPS 0x01
#define INT_WUFS 0x02
#define INT_TAP_SINGLE 0x04
#define INT_TAP_DOUBLE 0x08
#define INT_DRDY 0x10
void mw_acc_init_i2c(void);
void mw_acc_disable_i2c(void);
void mw_acc_i2c_read(const uint8_t RegisterAddress, uint8_t *pData, const uint8_t Length);
void mw_acc_i2c_write(uint8_t RegisterAddress, uint8_t *pData, uint8_t Length);
void mw_acc_init(void);
void mw_acc_enable(void);
void mw_acc_disable(void);
void mw_acc_read(int16_t *x, int16_t *y, int16_t *z);
void mw_acc_handle_irq(void);
#endif

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#include <msp430.h>
#include <msp430xgeneric.h>
#include <stdint.h>
#include "mw_main.h"
#define HARDWARE_CFG_INPUT_CHANNEL ( ADC12INCH_13 )
#define BATTERY_SENSE_INPUT_CHANNEL ( ADC12INCH_15 )
#define LIGHT_SENSE_INPUT_CHANNEL ( ADC12INCH_1 )
#define ENABLE_ADC() { ADC12CTL0 |= ADC12ON; ADC12CTL0 |= ADC12ENC + ADC12SC; }
#define DISABLE_ADC() { ADC12CTL0 &= ~ADC12ENC; ADC12CTL0 &= ~ADC12ON; }
#define CLEAR_START_ADDR() { ADC12CTL1 &= 0x0FFF; }
const double CONVERSION_FACTOR_BATTERY = ((24300.0+38300.0)*2.5*1000.0)/(4095.0*24300.0);
#define BATTERY_FULL_LEVEL (4140)
#define BATTERY_CRITICAL_LEVEL (3300)
#define BATTERY_LEVEL_RANGE (BATTERY_FULL_LEVEL - BATTERY_CRITICAL_LEVEL)
/*! conversion factor */
const double CONVERSION_FACTOR = 2.5*10000.0/4096.0;
void mw_init_adc(void)
{
REFCTL0 = REFMSTR | REFTCOFF;
LIGHT_SENSE_INIT();
BATTERY_SENSE_INIT();
HARDWARE_CFG_SENSE_INIT();
/* allow conditional request for modosc */
UCSCTL8 |= MODOSCREQEN;
/* select ADC12SC bit as sample and hold source (00)
* and use pulse mode
* use modosc / 8 because frequency must be 0.45 MHz to 2.7 MHz (0.625 MHz)
*/
ADC12CTL1 = ADC12CSTARTADD_0 + ADC12SHP + ADC12SSEL_0 + ADC12DIV_7;
/* 12 bit resolution, only use reference when doing a conversion */
ADC12CTL2 = ADC12TCOFF + ADC12RES_2 + ADC12REFBURST;
/* setup input channels */
ADC12MCTL0 = HARDWARE_CFG_INPUT_CHANNEL + ADC12EOS;
ADC12MCTL1 = BATTERY_SENSE_INPUT_CHANNEL + ADC12EOS;
ADC12MCTL2 = LIGHT_SENSE_INPUT_CHANNEL + ADC12EOS;
}
unsigned int mw_get_battery_adc_val(void)
{
BATTERY_SENSE_ENABLE();
/* low_bat_en assertion to bat_sense valid is ~100 ns */
/* Start battery sense conversion */
CLEAR_START_ADDR();
ADC12CTL1 |= ADC12CSTARTADD_1;
ENABLE_ADC();
/* WaitForAdcBusy(); */
while (ADC12CTL1 & ADC12BUSY)
nop();
/* Convert the ADC count for the battery input into a voltage
* ADC12MEM1: Counts Battery Voltage in ADC counts
* Result: Battery voltage in millivolts */
BATTERY_SENSE_DISABLE();
return (unsigned int)(CONVERSION_FACTOR_BATTERY * (double)ADC12MEM1);
}
uint8_t mw_get_battery_percentage_from_val(unsigned int BattVal)
{
if (BattVal > BATTERY_FULL_LEVEL)
BattVal = BATTERY_FULL_LEVEL;
if (BattVal < BATTERY_CRITICAL_LEVEL)
BattVal = 0;
else
BattVal -= BATTERY_CRITICAL_LEVEL;
BattVal = (BattVal > 0) ? (BattVal * 10 / (BATTERY_LEVEL_RANGE / 10)) : 0;
return (unsigned char)BattVal;
}
uint16_t mw_get_amblight_adc_val(void)
{
LIGHT_SENSE_ENABLE();
CLEAR_START_ADDR();
ADC12CTL1 |= ADC12CSTARTADD_2;
ENABLE_ADC();
/* WaitForAdcBusy(); */
while (ADC12CTL1 & ADC12BUSY)
nop();
LIGHT_SENSE_DISABLE();
return ADC12MEM2;
}

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#ifndef _MW_ADC_H
#define _MW_ADC_H
void mw_init_adc(void);
unsigned int mw_get_battery_adc_val(void);
uint8_t mw_get_battery_percentage_from_val(unsigned int BatVal);
uint16_t mw_get_amblight_adc_val(void);
#endif

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#include <msp430.h>
#include <msp430xgeneric.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include "mw_main.h"
#include "mw_uart.h"
#include "mw_bt.h"
#include "bt_hci.h"
#include "bt_l2cap.h"
#include "bluetooth_init_cc256x.h"
static char bt_rx_buf[BT_RX_MAX_SIZE];
static unsigned char bt_rx_buf_wpos = 0;
static unsigned char bt_rx_buf_rpos = 0;
static uint8_t mw_bt_enabled = 0;
int mw_bt_get_rxbuf_len(void)
{
if (bt_rx_buf_rpos > bt_rx_buf_wpos)
return (BT_RX_MAX_SIZE - bt_rx_buf_rpos) + bt_rx_buf_wpos;
else
return bt_rx_buf_wpos - bt_rx_buf_rpos;
}
const unsigned char *mw_bt_get_rx_buf(unsigned char **rpos, unsigned char *len)
{
*rpos = &bt_rx_buf_rpos;
if (bt_rx_buf_rpos > bt_rx_buf_wpos)
*len = (BT_RX_MAX_SIZE - bt_rx_buf_rpos) + bt_rx_buf_wpos;
else
*len = bt_rx_buf_wpos - bt_rx_buf_rpos;
// if we reach high water mark raise RTS to stop more data
if (*len > (BT_RX_MAX_SIZE-(BT_RX_MAX_SIZE/10))) {
debug_uart_tx("BT UART RTS\n");
BT_IO_POUT |= BT_IO_RTS; // low == ready, high == !ready
} else {
BT_IO_POUT &= ~BT_IO_RTS; // low == ready, high == !ready
}
return (unsigned char *)bt_rx_buf;
}
#pragma vector=USCI_A1_VECTOR
__interrupt void UCA1_ISR (void)
{
switch (UCA1IV) {
case 2: // RXIFG
/* clear IRQ flag */
//UCA1IFG &= ~UCRXIFG;
/* wake up to handle the received char */
if (UCA1STAT & UCRXERR) {
debug_uart_tx("BT UART RXERR: ");
if (UCA1STAT & UCOE)
debug_uart_tx("overrun ");
if (UCA1STAT & UCPE)
debug_uart_tx("parity err ");
if (UCA1STAT & UCFE)
debug_uart_tx("frm-err ");
debug_uart_tx("\n");
}
bt_rx_buf[bt_rx_buf_wpos++] = UCA1RXBUF;
bt_rx_buf_wpos %= BT_RX_MAX_SIZE;
// LPM3_EXIT;
LPM3_EXIT_ISR();
_event_src |= BT_UART_RCV_EVENT;
break;
case 4: // TXIFG
debug_uart_tx("BT UART TX IRQ - huh?\n");
break;
default:
break;
};
}
void mw_init_bt_uart(const bt_uart_baud_t baud)
{
UCA1CTL1 = UCSWRST;
UCA1CTL1 |= UCSSEL__SMCLK;
switch (baud) {
case BT_UART_BD115200:
default:
UCA1BR0 = 138;
UCA1MCTL = UCBRS_7 + UCBRF_0;
break;
};
UCA1STAT = 0;
// UCA1CTL0 = UCMODE_0; // UART mode
// UCA1CTL0 &= ~UC7BIT; // 8bit char
//UCA1CTL0 |= UCRXEIE;
UCA1CTL1 &= ~UCSWRST;
/* clear interrup flags */
UCA1IFG = 0;
UCA1IE = UCRXIE;
}
#if 0 // Does never finish, presumably trigger does not trigger, unknown :(
void mw_bt_uart_tx(const void *buf, const unsigned int len)
{
UCA1IE &= UCTXIE;
DMACTL0 = DMA0TSEL_21;
DMA0DA = (unsigned int) &UCA1TXBUF;
DMA0SA = (uint32_t) buf;
DMA0SZ = len;
//DMA0CTL = 0x03F0;
DMA0CTL = DMADT_1 | DMASRCINCR_3 | DMASBDB | DMALEVEL | DMAIE;
UCA1IFG &= ~UCTXIFG;
DMA0CTL |= DMAEN;
while ((DMA0CTL & DMAIFG) == 0 && (DMA0CTL & DMAABORT) == 0)
nop();
}
#else
int mw_bt_uart_tx(const void *buf, const unsigned int len)
{
unsigned int pos, i;
// char txstr[8];
pos = 0;
// debug_uart_tx("BT tx: ");
while (pos < len) {
// watch for CTS to be low
i = 0;
while ((BT_IO_PIN & BT_IO_CTS) && (i < 1000)) {
__delay_cycles(16000);
i++;
if (i >= 1000)
return -1;
// nop();
}
// do not start a transfer if UART is busy, e.g. rx-ing
while (UCA1STAT & UCBUSY)
nop();
UCA1TXBUF = *(unsigned char *) (buf+pos);
// debug_uart_tx_char(*(unsigned char *) (buf+pos));
// snprintf(txstr, 8, "0x%02x ", *(unsigned char *) (buf+pos));
// debug_uart_tx(txstr);
pos++;
while ((UCA1IFG & UCTXIFG) == 0)
nop();
}
while (UCA1STAT & UCBUSY)
nop();
return len;
}
#endif
static int load_cc256x_init_script(void)
{
uint32_t pos;
unsigned char *tptr;
int tlen;
pos = 0;
while (pos < cc256x_init_script_size) {
if (_event_src != 0)
handle_event();
tptr = (unsigned char *)(cc256x_init_script + pos);
tlen = mw_bt_uart_tx(tptr, 4 + tptr[3]);
if (tlen < 0)
return -1;
pos += tlen /*4 + tptr[3]*/;
// each init script part is one HCI command so wait for reply
if (_event_src != 0)
handle_event();
}
return 0;
}
void mw_enable_bt(void)
{
int i;
/* make sure it resets */
BT_SHUTDOWN();
__delay_cycles(16000);
/* enable 32kHz ACLK output to BT module */
P11DIR |= BIT0;
P11SEL |= BIT0;
// wait for clock to stabilize
__delay_cycles(16000);
// disable the IRQ on CTS, later used to get a wakeup IRQ from eHCILL
// will be enabled when going to sleep
P1IE &= ~BT_IO_CTS;
P1IES &= ~BT_IO_CTS;
BT_IO_PDIR &= ~(BT_IO_CTS | BT_IO_PIN1 | BT_IO_PIN2 | BT_IO_CLKREQ);
BT_IO_PDIR |= BT_IO_RTS;
BT_IO_POUT &= ~(BT_IO_CTS | BT_IO_PIN1 | BT_IO_PIN2 | BT_IO_CLKREQ);
BT_IO_POUT &= ~BT_IO_RTS; // low == ready, high == !ready
BT_IO_REN |= BT_IO_CTS; // enable pull-down on CTS, POUT-CTS is 0 already
/* setup UART pins */
BT_UART_PSEL |= BT_UART_TX_PIN | BT_UART_RX_PIN;
// P5OUT |= BT_UART_TX_PIN | BT_UART_RX_PIN;
// P5REN |= BT_UART_TX_PIN | BT_UART_RX_PIN;
mw_init_bt_uart(BT_UART_BD115200);
bt_rx_buf_wpos = 0;
bt_rx_buf_rpos = 0;
/* release BT reset pin */
BT_ENABLE();
for (i=0; i<1000; i++) {
__delay_cycles(16000);
if ((BT_IO_PIN & BT_IO_CTS) == 0) // when CTS goes low module is ready
break;
}
if (i>=1000) {
debug_uart_tx("Timeout waiting for CC256x to lower CTS\n");
mw_bt_enabled = 0;
} else {
debug_uart_tx("CC256x CTS low - uploading init\n");
// the init script consists of HCI cmds so HCI must be setup before
bt_hci_init();
// give it some more time before anyone sends data
for (i=0; i<10; i++) {
__delay_cycles(16000);
}
if (load_cc256x_init_script() < 0) {
debug_uart_tx("init upload failed!\n");
return;
}
__delay_cycles(32000);
debug_uart_tx("init uploaded\n");
init_l2cap();
if (_event_src != 0)
handle_event();
mw_bt_enabled = 1;
}
}
void mw_disable_bt(void)
{
mw_bt_enabled = 0;
// disable the IRQ on CTS
P1IE &= ~BT_IO_CTS;
P1IES &= ~BT_IO_CTS;
// BT_IO_REN &= ~BT_IO_CTS; // disable pull-down on CTS
P1IFG &= ~BT_IO_CTS;
/* disable UART RX interrupt */
UCA1IE &= ~UCRXIE;
/* disable UART pins */
BT_UART_PSEL &= ~(BT_UART_TX_PIN | BT_UART_RX_PIN);
/* set BT reset pin */
BT_SHUTDOWN();
/* disable 32kHz ACLK output to BT module */
P11DIR &= ~BIT0;
P11SEL &= ~BIT0;
/* make all I/O Pins inputs so we do not drive against a "deaf" module */
BT_IO_PDIR &= ~(BT_IO_RTS | BT_IO_CTS | BT_IO_PIN1 | BT_IO_PIN2 | BT_IO_CLKREQ);
BT_IO_POUT &= ~(BT_IO_RTS | BT_IO_CTS | BT_IO_PIN1 | BT_IO_PIN2 | BT_IO_CLKREQ);
}
uint8_t mw_bt_is_enabled(void)
{
return mw_bt_enabled;
}

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#ifndef _MW_BT_H
#define _MW_BT_H
#define BT_RST_PIN BIT3
#define BT_RST_PSEL P10SEL
#define BT_RST_POUT P10OUT
#define BT_RST_PDIR P10DIR
#define BT_IO_PSEL P1SEL
#define BT_IO_RTS BIT0
#define BT_IO_CTS BIT3
#define BT_IO_POUT P1OUT
#define BT_IO_PIN P1IN
#define BT_IO_PDIR P1DIR
#define BT_IO_REN P1REN
#define BT_IO_PIN1 BIT5
#define BT_IO_PIN2 BIT6
#define BT_IO_CLKREQ BIT4
#define BT_SHUTDOWN() { BT_RST_POUT &= ~BT_RST_PIN; }
#define BT_ENABLE() { BT_RST_POUT |= BT_RST_PIN; }
#define BT_UART_PSEL P5SEL
#define BT_UART_PDIR P5DIR
#define BT_UART_REN P5REN
#define BT_UART_POUT P5OUT
#define BT_UART_TX_PIN BIT6
#define BT_UART_RX_PIN BIT7
#define CONFIG_BT_PINS() { \
BT_RST_PSEL &= ~BT_RST_PIN; \
BT_RST_PDIR |= BT_RST_PIN; \
BT_SHUTDOWN(); \
BT_IO_PSEL &= ~(BT_IO_RTS | BT_IO_CTS | BT_IO_PIN1 | BT_IO_PIN2 | BT_IO_CLKREQ); \
BT_IO_PDIR &= ~(BT_IO_RTS | BT_IO_CTS | BT_IO_PIN1 | BT_IO_PIN2 | BT_IO_CLKREQ); \
BT_IO_POUT &= ~(BT_IO_RTS | BT_IO_CTS | BT_IO_PIN1 | BT_IO_PIN2 | BT_IO_CLKREQ); \
BT_UART_PSEL &= ~(BT_UART_TX_PIN | BT_UART_RX_PIN); \
BT_UART_PDIR &= ~(BT_UART_TX_PIN | BT_UART_RX_PIN); \
BT_UART_REN |= BT_UART_TX_PIN | BT_UART_RX_PIN; \
BT_UART_POUT |= BT_UART_TX_PIN | BT_UART_RX_PIN; \
}
void mw_enable_bt(void);
void mw_disable_bt(void);
typedef enum {
BT_UART_BD19200 = 0,
BT_UART_BD38400,
BT_UART_BD57600,
BT_UART_BD115200,
BT_UART_BD234000,
} bt_uart_baud_t;
#define BT_MW_DEVICE_CLASS 0x842704 /* Limited discovery, Rendering, Information, Wearable, Wrist Watch */
#define BT_RX_MAX_SIZE 255
void mw_init_bt_uart(const bt_uart_baud_t baud);
int mw_bt_uart_tx(const void *buf, const unsigned int len);
// extern char BT_UART_RX_CHAR;
int mw_bt_get_rxbuf_len(void);
const unsigned char *mw_bt_get_rx_buf(unsigned char **rpos, unsigned char *len);
unsigned char bt_feed_packet_data(unsigned char pdata);
uint8_t mw_bt_is_enabled(void);
#endif

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#include <msp430.h>
#include <stdint.h>
#include "mw_main.h"
#include "mw_lcd.h"
#include "mw_uart.h"
// SMCLK = 16MHz -> divide by 16 to get 1 MHz SPI clock,
// 1MHz maximum according to LCD spec
//#define SPI_PRESCALE_L 0x10
// currently we only run @1MHz
#define SPI_PRESCALE_L 0x10
#define SPI_PRESCALE_H 0x00
#define LCD_STATIC_CMD 0x00
#define LCD_WRITE_CMD 0x01
#define LCD_CLEAR_CMD 0x04
static const unsigned char LCD_CLEAR_COMMAND[] = {LCD_CLEAR_CMD, 0x00};
#define LCD_CLEAR_CMD_SIZE 0x02
static const unsigned char LCD_STATIC_COMMAND[] = {LCD_STATIC_CMD, 0x00};
#define LCD_STATIC_CMD_SIZE 0x02
/* the LCD frame buffer, 96 lines */
tLcdLine lcd_buf[96];
#define LCD_DMA
/* errata - DMA variables cannot be function scope */
#ifdef LCD_DMA
static unsigned char LcdDmaBusy = 0;
#endif
void memfill(void *target, unsigned char val, unsigned int count)
{
while (count--) {
*(unsigned char *)(target+count) = val;
}
}
void mw_lcd_init(void)
{
int i;
/* basic I/O setup */
ENABLE_LCD_POWER();
CONFIG_LCD_PINS();
// DISABLE_LCD_ENABLE();
ENABLE_LCD_ENABLE();
/* Put state machine in reset while it is configured */
LCD_SPI_UCBxCTL1 |= UCSWRST;
/*
* 3-pin, 8-bit SPI master, Clock polarity low
* Clock phase set, least sig bit first
* SMCLK is the clock source
* set the clock prescaler
*/
LCD_SPI_UCBxCTL0 |= UCMST+ UCCKPH + UCSYNC;
LCD_SPI_UCBxCTL1 |= UCSSEL_2;
LCD_SPI_UCBxBR0 = SPI_PRESCALE_L;
LCD_SPI_UCBxBR1 = SPI_PRESCALE_H;
/* remove reset */
LCD_SPI_UCBxCTL1 &= ~UCSWRST;
/* pre-fill the frame-buffer */
for (i=0; i<96; i++) {
lcd_buf[i].Row = i+1;
memfill(lcd_buf[i].Data, 0xff, 12);
// lcd_buf[i].Data[0] = i;
lcd_buf[i].Dummy = 0x00;
};
}
static void mw_lcd_write_line(const void *pData, unsigned char Size)
{
#ifndef xLCD_DMA
unsigned char Index;
#endif
LCD_CS_ASSERT();
#ifdef xLCD_DMA
LcdDmaBusy = 1;
/* USCIB0 TXIFG is the DMA trigger
* DMACTL1 controls dma2 and [dma3]
*/
DMACTL1 = DMA2TSEL_19;
DMA2SA = (unsigned int) pData;
DMA2DA = (unsigned int) &LCD_SPI_UCBxTXBUF;
DMA2SZ = (unsigned int)Size;
/*
* single transfer, increment source address, source byte and dest byte,
* level sensitive, enable interrupt, clear interrupt flag
*/
DMA2CTL = DMADT_0 + DMASRCINCR_3 + DMASBDB + DMALEVEL + DMAIE;
/* start the transfer */
DMA2CTL |= DMAEN;
while (LcdDmaBusy)
nop();
#else
// debug_uart_tx("+wl1");
for ( Index = 0; Index < Size; Index++ ) {
LCD_SPI_UCBxTXBUF = ((unsigned char *)pData)[Index];
// debug_uart_tx(".");
while (!(LCD_SPI_UCBxIFG & UCTXIFG)) {
// debug_uart_tx("+");
nop();
}
}
// debug_uart_tx("\n+wl2\n");
#endif
/* wait for shift to complete ( ~3 us ) */
while (LCD_SPI_UCBxSTAT & 0x01) {
nop();
// debug_uart_tx(".");
};
/* now the chip select can be deasserted */
LCD_CS_DEASSERT();
// debug_uart_tx("\n-wl\n");
}
void mw_lcd_static_mode(void)
{
mw_lcd_write_line(LCD_STATIC_COMMAND, LCD_STATIC_CMD_SIZE);
}
void mw_lcd_clear(void)
{
unsigned char i;
mw_lcd_write_line(LCD_CLEAR_COMMAND, LCD_CLEAR_CMD_SIZE);
/* pre-fill the frame-buffer */
for (i=0; i<96; i++) {
memfill(lcd_buf[i].Data, 0xff, 12);
};
}
void mw_lcd_clear_fb(void)
{
unsigned char i;
/* pre-fill the frame-buffer */
for (i=0; i<96; i++) {
#if LCD_BLACK == 0
memfill(lcd_buf[i].Data, 0xff, 12);
#else
memfill(lcd_buf[i].Data, 0x00, 12);
#endif
};
}
#pragma vector=DMA_VECTOR
__interrupt void DMA_ISR (void)
{
switch (DMAIV) {
case 0:
DMA0CTL &= ~DMAEN; // disable
DMA0CTL &= ~DMAIFG; // clear IRQ flag
debug_uart_tx("DMA0 IRQ\n");
break;
case 2:
debug_uart_tx("DMA1 IRQ\n");
break;
case 4:
debug_uart_tx("DMA2b IRQ\n");
break;
case 6:
DMA2CTL &= ~DMAEN; // disable
DMA2CTL &= ~DMAIFG; // clear IRQ flag
#ifdef LCD_DMA
LcdDmaBusy = 0;
#endif
//LED7_TOGGLE();
// debug_uart_tx("DMA2 IRQ\n");
break;
}
}
/* writes the complete internal framebuffer to the LCD */
void mw_lcd_update_screen(void)
{
//#ifndef LCD_DMA
unsigned int i,j;
//#endif
// debug_uart_tx("uscr1\n");
// invert the buffer
if (0) {
for (i=0; i<96; i++) {
for ( j = 0; j < 12; j++ ) {
lcd_buf[i].Data[j] = ~lcd_buf[i].Data[j];
}
}
}
LCD_CS_ASSERT();
/* send WRITE command */
LCD_SPI_UCBxTXBUF = LCD_WRITE_CMD;
while (!(LCD_SPI_UCBxIFG & UCTXIFG))
nop();
// debug_uart_tx("uscr2\n");
#ifdef LCD_DMA
LcdDmaBusy = 1;
/* USCIB0 TXIFG is the DMA trigger
* DMACTL1 controls dma2 and [dma3]
*/
DMACTL1 = DMA2TSEL_19;
DMA2SA = (unsigned int) lcd_buf;
DMA2DA = (unsigned int) &LCD_SPI_UCBxTXBUF;
DMA2SZ = 96 * sizeof(tLcdLine);
/*
* single transfer, increment source address, source byte and dest byte,
* level sensitive, enable interrupt, clear interrupt flag
*/
DMA2CTL = DMADT_0 + DMASRCINCR_3 + DMASBDB + DMALEVEL + DMAIE;
/* start the transfer */
DMA2CTL |= DMAEN;
// debug_uart_tx("uscr3\n");
// LED7_OFF();
while (LcdDmaBusy)
nop();
// debug_uart_tx("uscr4\n");
#else
for (i=0; i<96; i++) {
for ( j = 0; j < sizeof(tLcdLine); j++ ) {
LCD_SPI_UCBxTXBUF = ((unsigned char *)(&lcd_buf[i]))[j];
while (!(LCD_SPI_UCBxIFG & UCTXIFG))
nop();
}
}
#endif
/* send final trailer byte */
LCD_SPI_UCBxTXBUF = 0x00;
while (!(LCD_SPI_UCBxIFG & UCTXIFG))
nop();
// debug_uart_tx("uscr5\n");
/* wait for shift to complete ( ~3 us ) */
while (LCD_SPI_UCBxSTAT & 0x01)
nop();
// debug_uart_tx("uscr6\n");
LCD_CS_DEASSERT();
mw_lcd_static_mode();
}
void mw_lcd_draw_pixel(const uint8_t x, const uint8_t y, const uint8_t color)
{
switch (color) {
case 1:
lcd_buf[y].Data[x/8] |= 1 << (x % 8);
break;
case 0:
lcd_buf[y].Data[x/8] &= ~(1 << (x % 8));
break;
case 2:
lcd_buf[y].Data[x/8] ^= 1 << (x % 8);
break;
}
}

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#ifndef _MW_LCD_H
#define _MW_LCD_H
typedef struct
{
unsigned char Row; /* row number for LCD command */
unsigned char Data[12]; /* 12*8 = 96bit */
unsigned char Dummy; /* 0x00 dummy byte to latch data into LCD */
} tLcdLine;
extern tLcdLine lcd_buf[];
void memfill(void *target, unsigned char val, unsigned int count);
void mw_lcd_init(void);
void mw_lcd_clear(void);
void mw_lcd_clear_fb(void);
void mw_lcd_update_screen(void);
#if 0
#define LCD_BLACK 0
#define LCD_WHITE 1
#else
#define LCD_BLACK 1
#define LCD_WHITE 0
#endif
#define LCD_XOR 2
void mw_lcd_draw_pixel(const uint8_t x, const uint8_t y, const uint8_t color);
#endif

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#include <msp430.h>
#include <msp430xgeneric.h>
#include <stdio.h>
#include <string.h>
#include "F5xx_F6xx_Core_Lib/HAL_PMM.h"
#include "F5xx_F6xx_Core_Lib/HAL_UCS.h"
#include "mw_main.h"
#include "mw_uart.h"
#include "mw_lcd.h"
#include "mw_bt.h"
#include "mw_adc.h"
#include "mw_bt.h"
#include "mw_acc.h"
#include "bt_hci.h"
#include "bt_l2cap.h"
#include "oswald_main.h"
#include "oswald_hal.h"
#include "bluetooth_init_cc256x.h"
uint16_t _event_src = 0;
#define HARDWARE_REVISION_ADDRESS (0x1a07)
uint8_t GetMsp430HardwareRevision(void)
{
uint8_t *pDeviceType = (uint8_t *)(uint8_t *)HARDWARE_REVISION_ADDRESS;
return pDeviceType[0]+'1';
}
uint8_t DetermineErrata(void)
{
uint8_t Revision = GetMsp430HardwareRevision();
switch (Revision) {
case 'F':
case 'G':
case 'H':
return 0;
break;
default:
return 1;
break;
}
}
static void set16mhz(void)
{
UCSCTL0 = 0x00; // Set lowest possible DCOx, MODx
UCSCTL1 = DCORSEL_5; // Select suitable range
UCSCTL2 = 488 + FLLD_1; // Set DCO Multiplier
UCSCTL4 = SELA__XT1CLK | SELS__DCOCLKDIV | SELM__DCOCLKDIV ;
// Worst-case settling time for the DCO when the DCO range bits have been
// changed is n x 32 x 32 x f_FLL_reference. See UCS chapter in 5xx UG
// for optimization.
// 32 x 32 x / f_FLL_reference (32,768 Hz) = .03125 = t_DCO_settle
// t_DCO_settle / (1 / 18 MHz) = 562500 = counts_DCO_settle
// __delay_cycles(562500);
int i;
for (i=0;i<10;i++){
__delay_cycles(56250);
}
}
static unsigned char PMM15Check(void)
{
// First check if SVSL/SVML is configured for fast wake-up
if ((!(SVSMLCTL & SVSLE)) || ((SVSMLCTL & SVSLE) && (SVSMLCTL & SVSLFP)) ||
(!(SVSMLCTL & SVMLE)) || ((SVSMLCTL & SVMLE) && (SVSMLCTL & SVMLFP)))
{
// Next Check SVSH/SVMH settings to see if settings are affected by PMM15
if ((SVSMHCTL & SVSHE) && (!(SVSMHCTL & SVSHFP)))
{
if ( (!(SVSMHCTL & SVSHMD)) ||
((SVSMHCTL & SVSHMD) && (SVSMHCTL & SVSMHACE)) )
return 1; // SVSH affected configurations
}
if ((SVSMHCTL & SVMHE) && (!(SVSMHCTL & SVMHFP)) && (SVSMHCTL & SVSMHACE))
return 1; // SVMH affected configurations
}
return 0; // SVS/M settings not affected by PMM15
}
#define configCPU_CLOCK_HZ ((unsigned long) 16777216) /* 512*32768 */
#define configTICK_RATE_HZ ((unsigned int)1024)
#define ACLK_MULTIPLIER ((unsigned int)512)
static void setup_clocks(void)
{
unsigned long i;
SetVCore(PMMCOREV_2);
/* use external oscillator */
P7SEL |= BIT0 + BIT1;
#if 1
if ((UCSCTL6 & XT1DRIVE_3) != XT1DRIVE_3) {
UCSCTL6_L |= XT1DRIVE1_L + XT1DRIVE0_L;
}
i = 50000;
while ((SFRIFG1 & OFIFG) && i--) {
UCSCTL7 &= ~(DCOFFG + XT1LFOFFG + XT1HFOFFG + XT2OFFG);
SFRIFG1 &= ~OFIFG;
}
UCSCTL6 = (UCSCTL6 & ~(XT1DRIVE_3)) |(XT1DRIVE_0);
set16mhz();
UCSCTL8 |= SMCLKREQEN;
#else
// Startup LFXT1 32 kHz crystal
while (LFXT_Start_Timeout(XT1DRIVE_0, 50000) == UCS_STATUS_ERROR)
nop();
// select the sources for the FLL reference and ACLK
SELECT_ACLK(SELA__XT1CLK);
SELECT_FLLREF(SELREF__XT1CLK);
// 512 * 32768 = 16777216 / 1024
Init_FLL_Settle(configCPU_CLOCK_HZ/configTICK_RATE_HZ, ACLK_MULTIPLIER);
// Disable FLL loop control
// __bis_SR_register(SCG0);
#endif
// setup for quick wake up from interrupt and
// minimal power consumption in sleep mode
DISABLE_SVSL(); // SVS Low side is turned off
DISABLE_SVSL_RESET();
DISABLE_SVML(); // Monitor low side is turned off
DISABLE_SVML_INTERRUPT();
DISABLE_SVMH(); // Monitor high side is turned off
DISABLE_SVMH_INTERRUPT();
ENABLE_SVSH(); // SVS High side is turned on
ENABLE_SVSH_RESET(); // Enable POR on SVS Event
SVSH_ENABLED_IN_LPM_FULL_PERF(); // SVS high side Full perf mode,
// stays on in LPM3,enhanced protect
SVSL_ENABLED_IN_LPM_FAST_WAKE();
// Wait until high side, low side settled
while ((PMMIFG & SVSMLDLYIFG) == 0 && (PMMIFG & SVSMHDLYIFG) == 0)
nop();
CLEAR_PMM_IFGS();
while (PMM15Check());
// Errata PMM17
if (DetermineErrata()) {
*(unsigned int*)(0x0110) = 0x9602;
*(unsigned int*)(0x0112) |= 0x0800;
}
/* enable oscillator fault NMI IRQ */
// SFRIE1 = OFIE;
}
#if 0
#pragma vector=PWR_PORT_VECTOR
__interrupt void PWR_ISR (void)
{
/* clear all possible sources */
PWR_PORT_IFG &= ~(BAT_CHARGE_STAT1 | BAT_CHARGE_STAT2 | BAT_CHARGE_PWR_BIT);
_event_src |= POWER_SRC_EVENT;
LPM3_EXIT();
nop();
}
#endif
static void mw_init_vibrate_pwm(void)
{
#ifdef MW_DIGITAL_V2
// Start with P7.3 as an output
P7OUT &= ~BIT3; // Low when a digital output
P7SEL &= ~BIT3; // P7 option select = false
P7DIR |= BIT3; // P7 outputs
TA1CTL = 0;
// No expansion divide
TA1EX0 = 0;
// do a PWM with 64 total steps. This gives a count up of 32 and
// a count down of 32
TA1CCR0 = 31;
// Compare channel 2 is used as output
TA1CCTL2 = OUTMOD_6; // PWM output mode: 6 - toggle/set
TA1CCR2 = 10; // 10 is a 2/3 duty cycle
#endif
}
static void setup_pins(void)
{
CONFIG_SRAM_PINS();
CONFIGURE_BUTTON_PINS();
#ifdef MW_DEVBOARD_V2
CONFIG_LED_PINS(); // debug LEDs on devboard
#endif
DISABLE_LCD_LED(); // frontlight
CONFIG_DEBUG_PINS();
CONFIG_ACCELEROMETER_PINS();
//DISABLE_ACCELEROMETER_POWER(); // starts from config 5 and later
ENABLE_ACCELEROMETER_POWER(); // starts from config 5 and later
HARDWARE_CFG_SENSE_INIT();
APPLE_CONFIG();
APPLE_POWER_DISABLE();
CONFIG_BT_PINS();
// BT_CLK_REQ_CONFIG_AS_OUTPUT_LOW();
// BT_IO1_CONFIG_AS_OUTPUT_LOW();
// BT_IO2_CONFIG_AS_OUTPUT_LOW();
BT_CLK_REQ_CONFIG_AS_INPUT();
BT_IO1_CONFIG_AS_INPUT();
BT_IO2_CONFIG_AS_INPUT();
mw_disable_bt();
LIGHT_SENSE_INIT();
LIGHT_SENSOR_SHUTDOWN();
BATTERY_SENSE_INIT();
BATTERY_SENSE_DISABLE();
BAT_CHARGE_DIR &= ~(BAT_CHARGE_STAT1 | BAT_CHARGE_STAT2 | BAT_CHARGE_PWR_BIT);
BAT_CHARGE_OUT |= BAT_CHARGE_PWR_BIT | BAT_CHARGE_STAT1 | BAT_CHARGE_STAT2; // pull-up
BAT_CHARGE_REN |= BAT_CHARGE_PWR_BIT; // enable resistors
// BAT_CHARGE_IE |= BAT_CHARGE_PWR_BIT;
BAT_CHARGE_OUT |= BAT_CHARGE_ENABLE_PIN; // !CE, negative logic
BAT_CHARGE_DIR |= BAT_CHARGE_ENABLE_PIN;
/* disable reset function, enable NMI, do not enable NMI IRQ */
/* to avoid accidential reset on charger clip connect */
#ifndef MW_DEVBOARD_V2 // but only on real watch
SFRRPCR &= ~SYSRSTRE;
SFRRPCR |= SYSNMI;
#endif
/* allow debug UART */
/*
P10SEL &= ~(BIT6 | BIT7);
P10DIR |= BIT6 | BIT7;
P10OUT &= ~(BIT6 | BIT7);
*/
#ifndef MW_DEVBOARD_V2
ENABLE_MUX_OUTPUT_CONTROL();
#ifdef MW_DEBUG_UART
MUX_OUTPUT_SELECTS_SERIAL();
#else
MUX_OUTPUT_OFF();
#endif
#endif
}
#pragma vector=WDT_VECTOR
__interrupt void WDT_ISR (void)
{
/* eventually we will do something here, not for now */
_event_src |= WATCHDOG_EVENT;
nop();
}
static void setup_wdt(void)
{
#if 1
WDTCTL = WDTPW + WDTHOLD; // disable watchdog
#else
WDTCTL = WDT_ADLY_1000; // 1 second timeout
SFRIE1 |= WDTIE; // Enable WDT interrupt
#endif
}
#if 1
#pragma vector=UNMI_VECTOR
__interrupt void NMI_ISR (void)
{
#if defined MW_DEVBOARD_V2
LED7_TOGGLE();
debug_uart_tx_char('n');
#endif
while ((SFRIFG1 & OFIFG)) {
UCSCTL7 &= ~(DCOFFG + XT1LFOFFG + XT1HFOFFG + XT2OFFG);
SFRIFG1 &= ~OFIFG;
}
}
#endif
#pragma vector=RTC_VECTOR
__interrupt void RTC_ISR (void)
{
switch (RTCIV) {
case RTCIV_NONE:
debug_uart_tx("RTC none IRQ\n");
break;
case RTCIV_RTCRDYIFG:
case RTCIV_RTCTEVIFG:
case RTCIV_RTCAIFG:
case RTCIV_RT0PSIFG:
debug_uart_tx("RTC misc IRQ\n");
break;
case RTCIV_RT1PSIFG:
RTCPS1CTL &= ~RT1PSIFG;
_event_src |= RTC_1HZ_EVENT;
// LPM3_EXIT;
LPM3_EXIT_ISR();
#if defined MW_DEVBOARD_V2
LED7_TOGGLE();
#endif
break;
default:
break;
};
}
void setup_rtc(void)
{
// stop it
RTCCTL01 = RTCHOLD;
// calibration
RTCCTL2 = 0x00 & 0x3f;
RTCCTL2 |= RTCCALS;
// Set the counter for RTC mode
RTCCTL01 |= RTCMODE;
// set 128 Hz rate for prescale 0 interrupt
RTCPS0CTL |= RT0IP_7;
// enable 1 pulse per second interrupt using prescale 1
RTCPS1CTL |= RT1IP_6 | RT1PSIE;
// 1 Hz calibration output
RTCCTL23 |= RTCCALF_3;
// setting the peripheral selection bit makes the other I/O control a don't care
// P2.4 = 1 Hz RTC calibration output
// Direction needs to be set as output
RTC_1HZ_PORT_SEL |= RTC_1HZ_BIT;
RTC_1HZ_PORT_DIR |= RTC_1HZ_BIT;
RTCYEAR = (unsigned int) 2013;
RTCMON = (unsigned int) 1;
RTCDAY = (unsigned int) 1;
RTCDOW = (unsigned int) 2;
RTCHOUR = (unsigned int) 01;
RTCMIN = (unsigned int) 0;
RTCSEC = (unsigned int) 0;
// Enable the RTC
RTCCTL01 &= ~RTCHOLD;
nop();
}
#if defined MW_DEVBOARD_V2 || MW_DEBUG_UART
static void dbg_out_rtc(void)
{
char clk_str[16];
snprintf(clk_str, 16, "%02d:%02d.%02d %d\n", RTCHOUR, RTCMIN, RTCSEC, RTCDOW);
debug_uart_tx(clk_str);
}
#endif
static void handle_button_event(void)
{
unsigned char _button_state = 0;
#if 0
char clk_str[16];
snprintf(clk_str, 16, "0x%02x\n", _button_state);
debug_uart_tx(clk_str);
#endif
while (_button_state != (BUTTON_PORT_IN & ALL_BUTTONS)) {
__delay_cycles(562500);
_button_state = (BUTTON_PORT_IN & ALL_BUTTONS);
__delay_cycles(562500);
}
// BUTTON_PORT_IE |= INT_EDGE_SEL_BUTTONS;
if (_button_state & SW_A) {
debug_uart_tx("switch A\n");
oswald_handle_button_press(BUTTON_A);
}
if (_button_state & SW_B) {
debug_uart_tx("switch B\n");
oswald_handle_button_press(BUTTON_B);
}
if (_button_state & SW_C) {
debug_uart_tx("switch C\n");
oswald_handle_button_press(BUTTON_C);
}
if (_button_state & SW_D) {
debug_uart_tx("switch D\n");
oswald_handle_button_press(BUTTON_D);
}
if (_button_state & SW_E) {
debug_uart_tx("switch E\n");
oswald_handle_button_press(BUTTON_E);
}
if (_button_state & SW_F) {
debug_uart_tx("switch F\n");
oswald_handle_button_press(BUTTON_F);
}
}
void check_pwr_state(void)
{
if (BAT_CHARGE_IN & BAT_CHARGE_PWR_BIT) {
BAT_CHARGE_OUT |= BAT_CHARGE_ENABLE_PIN;
BAT_CHARGE_REN &= ~(BAT_CHARGE_STAT1 | BAT_CHARGE_STAT2); // disable pull-up
} else {
BAT_CHARGE_OUT &= ~BAT_CHARGE_ENABLE_PIN;
BAT_CHARGE_REN |= BAT_CHARGE_STAT1 | BAT_CHARGE_STAT2; // enable pull-up
}
}
static void handle_bt_uart_rx_event(void)
{
const unsigned char *rx;
unsigned char len, *rp, p;
rx = mw_bt_get_rx_buf(&rp, &len);
p = 0;
while (p < len) {
p += bt_feed_packet_data(rx[(*rp+p)%BT_RX_MAX_SIZE]);
}
// all consumed
*rp = (*rp + len) % BT_RX_MAX_SIZE;
}
#if defined MW_DEVBOARD_V2 || MW_DEBUG_UART
static void handle_uart_rx_event(void)
{
char c;
#ifndef CC256x_TRANSP
char tstr[255];
if (debug_uart_rx_char(&c)) {
debug_uart_tx_char(c);
if (c == 'a') {
debug_uart_tx("\nenabling ACC\n");
mw_acc_enable();
} else if (c == 'A') {
debug_uart_tx("\ndisabling ACC\n");
mw_acc_disable();
} else if (c == 'r') {
int16_t x,y,z;
debug_uart_tx("\nread ACC: ");
mw_acc_read(&x, &y, &z);
snprintf(tstr, 64, "x:%d y:%d z:%d\n", x,y,z);
debug_uart_tx(tstr);
} else if (c =='R') {
int16_t al;
al = mw_get_amblight_adc_val();
snprintf(tstr, 64, "light: %d\n", al);
debug_uart_tx(tstr);
} else if (c == 'b') {
debug_uart_tx("\nenabling BT\n");
mw_enable_bt();
} else if (c == 'B') {
debug_uart_tx("\ndisabling BT\n");
mw_disable_bt();
} else if (c == 'c') {
debug_uart_tx("\nCharger status: ");
snprintf(tstr, 16, "0x%04x 0x%04x ", BAT_CHARGE_IN, (BAT_CHARGE_IN & BAT_CHARGE_PWR_BIT));
debug_uart_tx(tstr);
if (BAT_CHARGE_IN & BAT_CHARGE_PWR_BIT)
debug_uart_tx("no ext pwr, ");
else
debug_uart_tx("ext pwr connected, ");
switch (BAT_CHARGE_IN & (BAT_CHARGE_STAT1 | BAT_CHARGE_STAT2)) {
case BAT_CHARGE_STAT1:
debug_uart_tx("charge done\n");
break;
case BAT_CHARGE_STAT2:
debug_uart_tx("fast charge\n");
break;
case (BAT_CHARGE_STAT1 | BAT_CHARGE_STAT2):
debug_uart_tx("suspend, sleep or fault\n");
break;
default:
debug_uart_tx("precharge\n");
break;
}
if (BAT_CHARGE_IN & BAT_CHARGE_ENABLE_PIN)
debug_uart_tx(" !charge\n");
else
debug_uart_tx(" charge\n");
} else if (c == 'd') {
debug_uart_tx("charging disabled\n");
BAT_CHARGE_OUT |= BAT_CHARGE_ENABLE_PIN;
} else if (c == 'e') {
debug_uart_tx("charging enabled\n");
BAT_CHARGE_OUT &= ~BAT_CHARGE_ENABLE_PIN;
} else if (c == 'l') {
debug_uart_tx("backlight LED on\n");
hal_lcd_set_backlight(TRUE);
} else if (c == 'L') {
debug_uart_tx("backlight LED off\n");
hal_lcd_set_backlight(FALSE);
} else if (c == 'u') {
mw_lcd_update_screen();
} else if (c == '+') {
nop();
} else if (c == '-') {
nop();
} else if (c == 'H') {
uint8_t dclass[3];
dclass[0] = BT_MW_DEVICE_CLASS & 0xff;
dclass[1] = (BT_MW_DEVICE_CLASS & 0xff00) >> 8;
dclass[2] = (BT_MW_DEVICE_CLASS & 0xff0000) >> 16;
debug_uart_tx("HCI reset\n");
bt_hci_cmd(HCI_HC_BB_OGF, HCI_RESET_OCF, 0, NULL);
bt_hci_cmd(HCI_HC_BB_OGF, HCI_W_COD_OCF, 3, dclass);
} else if (c == 'i') {
debug_uart_tx("Information:\n");
debug_uart_tx("Oswald ");
debug_uart_tx(MW_MAIN_VERSION);
debug_uart_tx("\n");
debug_uart_tx("Build #");
debug_uart_tx(BUILDNO);
debug_uart_tx("\n");
debug_uart_tx("BT V ");
debug_uart_tx(cc256x_version);
debug_uart_tx("\n");
debug_uart_tx("MCU Rev ");
debug_uart_tx_char(GetMsp430HardwareRevision());
debug_uart_tx("\n");
} else if (c == 'S') {
debug_uart_tx("Scan enable\n");
tstr[0] = HCI_BB_SCAN_INQUIRY | HCI_BB_SCAN_PAGE;
bt_hci_cmd(HCI_HC_BB_OGF, HCI_W_SCAN_EN_OCF, 1, (uint8_t *)tstr);
} else if (c == 'h') {
RTCHOUR++;
if (RTCHOUR > 23)
RTCHOUR = 0;
} else if (c == 'm') {
RTCMIN++;
if (RTCMIN > 59)
RTCMIN = 0;
} else if (c == 'N') {
debug_uart_tx("Set name\n");
tstr[0] = 'O';
tstr[1] = 's';
tstr[2] = 'w';
tstr[3] = 'a';
tstr[4] = 'l';
tstr[5] = 'd';
tstr[6] = 0x00;
bt_hci_cmd(HCI_HC_BB_OGF, HCI_W_LOCAL_NAME_OCF, 0x07, (uint8_t *)tstr);
} else if (c == 'R') {
bt_hci_cmd(HCI_INFO_PARAM_OGF, HCI_R_BD_ADDR_OCF, 0, NULL);
}
}
#endif
}
#endif
void start_timer(int cycles)
{
TA0EX0 = TAIDEX_0;
TA0CTL = TASSEL_1 | TACLR | MC__STOP; // SMCLK, clear TAR
TA0CCTL0 = CCIE; // CCR0 interrupt enabled
TA0CCR0 = cycles;
TA0CTL |= MC_1; // Start Timer_A in continuous mode
}
void stop_timer(void)
{
TA0CCTL0 &= ~CCIE; // CCR0 interrupt enabled
TA0CTL = MC__STOP; // Start Timer_A in continuous mode
}
// Timer A0 interrupt service routine
#pragma vector=TIMER0_A0_VECTOR
__interrupt void TIMER0_A0_ISR (void)
{
TA0CTL &= ~(TAIFG);
#if defined xMW_DEVBOARD_V2
LED6_TOGGLE();
#endif
_event_src |= TIMER_500MS_EVENT | TIMER_100MS_EVENT;
// LPM3_EXIT;
LPM3_EXIT_ISR();
}
uint8_t handle_event(void)
{
#if defined MW_DEVBOARD_V2 || MW_DEBUG_UART
char tstr[64];
#endif
if (_event_src == 0)
return 1;
while (_event_src != 0) {
if (_event_src & WATCHDOG_EVENT) {
_event_src &= ~WATCHDOG_EVENT;
debug_uart_tx_char('w');
} else if (_event_src & RTC_1HZ_EVENT) {
_event_src &= ~RTC_1HZ_EVENT;
check_pwr_state();
oswald_one_second_tick();
#if defined MW_DEVBOARD_V2 || MW_DEBUG_UART
dbg_out_rtc();
#endif
} else if (_event_src & BT_UART_RCV_EVENT) {
_event_src &= ~BT_UART_RCV_EVENT;
handle_bt_uart_rx_event();
} else if (_event_src & BT_UART_WAKEUP_EVENT) {
_event_src &= ~BT_UART_WAKEUP_EVENT;
bt_hci_ehcill_wake();
} else if (_event_src & DBG_UART_RCV_EVENT) {
_event_src &= ~DBG_UART_RCV_EVENT;
#if defined MW_DEVBOARD_V2 || MW_DEBUG_UART
handle_uart_rx_event();
#endif
} else if (_event_src & BUTTON_EVENT) {
_event_src &= ~BUTTON_EVENT;
handle_button_event();
} else if (_event_src & TIMER_500MS_EVENT) {
_event_src &= ~TIMER_500MS_EVENT;
oswald_halfsecond_tick();
} else if (_event_src & TIMER_100MS_EVENT) {
_event_src &= ~TIMER_100MS_EVENT;
oswald_centisecond_tick();
} else if (_event_src & ACCEL_EVENT) {
_event_src &= ~ACCEL_EVENT;
mw_acc_handle_irq();
} else {
#if defined MW_DEVBOARD_V2 || MW_DEBUG_UART
snprintf(tstr, 64, "unhandled event in 0x%04x\n", _event_src);
debug_uart_tx(tstr);
#endif
}
}
return 0;
}
#pragma vector=BUTTON_PORT_VECTOR
__interrupt void BUTTON_ISR (void)
{
// LPM3_EXIT;
LPM3_EXIT_ISR();
BUTTON_PORT_IFG &= ~ALL_BUTTONS;
// BUTTON_PORT_IE &= ~INT_EDGE_SEL_BUTTONS;
_event_src |= BUTTON_EVENT;
//_button_state = (BUTTON_PORT_IN & ALL_BUTTONS);
}
#pragma vector=PORT1_VECTOR
__interrupt void PORT1_GPIO_ISR (void)
{
if (P1IFG & BT_IO_CTS) {
//LPM3_EXIT;
LPM3_EXIT_ISR();
P1IE &= ~BT_IO_CTS;
P1IFG &= ~BT_IO_CTS;
debug_uart_tx("BT CTS irq\n");
_event_src |= BT_UART_WAKEUP_EVENT;
// bt_hci_ehcill_wake();
} else if (P1IFG & ACCELEROMETER_INT_PIN) {
//LPM3_EXIT;
LPM3_EXIT_ISR();
P1IFG &= ~ACCELEROMETER_INT_PIN;
// debug_uart_tx("ACC irq\n");
_event_src |= ACCEL_EVENT;
}
}
#if 0
#pragma vector=NOVECTOR
__interrupt void UNEXP_ISR (void)
{
debug_uart_tx("unexpected IRQ occured\n");
}
#endif
int main(void)
{
setup_wdt();
setup_pins();
setup_clocks();
setup_rtc();
/* enable interrupts, we will need them! */
__enable_interrupt();
#if defined MW_DEVBOARD_V2 || MW_DEBUG_UART
init_debug_uart();
debug_uart_tx("\nOswald on MetaWatch\n");
#endif
mw_lcd_init();
mw_lcd_clear();
mw_lcd_update_screen();
mw_init_adc();
mw_init_vibrate_pwm();
oswald_set_time(RTCHOUR, RTCMIN, RTCSEC, TRUE);
oswald_set_date(RTCDAY, RTCMON, RTCYEAR, TRUE);
oswald_init();
while (1) {
/* handle pending events */
handle_event();
/* enter LPM3 sleep mode waiting for interrupt */
/* errata PMM11 + PMM12 - divide MCLK before going to sleep */
if (DetermineErrata()) {
MCLK_DIV(2);
nop();
}
LPM3;
nop();
if (DetermineErrata()) {
__delay_cycles(100);
MCLK_DIV(1);
}
};
return 0;
}

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#ifndef _GCCFWTEST_LCD_H
#define _GCCFWTEST_LCD_H
#define MW_MAIN_VERSION "MW v0.4"
#if defined MW_DEVBOARD_V2
#include "hal_devboard_v2_defs.h"
#elif defined MW_DIGITAL_V2
#include "hal_digital_v2_defs.h"
#else
#error "Define a watch type!"
#endif
#include "hal_io_macros.h"
#define LPM3_EXIT_ISR() { _BIC_SR_IRQ(SCG1+OSCOFF+CPUOFF); nop(); }
#define WATCHDOG_EVENT 1 << 0
#define RTC_1HZ_EVENT 1 << 1
#define DBG_UART_RCV_EVENT 1 << 2
#define BUTTON_EVENT 1 << 3
#define TIMER_500MS_EVENT 1 << 4
#define TIMER_100MS_EVENT 1 << 5
#define POWER_SRC_EVENT 1 << 6
#define BT_UART_RCV_EVENT 1 << 7
#define BT_UART_WAKEUP_EVENT 1 << 8
#define ACCEL_EVENT 1 << 9
extern unsigned int _event_src;
//#define TIMER_500MS_CYCLES 32768
#define TIMER_500MS_CYCLES 16384
#define TIMER_100MS_CYCLES 327
void start_timer(int cycles);
void stop_timer(void);
uint8_t handle_event(void);
#endif

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#include <msp430.h>
#include <stdint.h>
#include <stdio.h>
#include <ctype.h>
#include "mw_main.h"
#include "mw_uart.h"
static char UART_RX_CHAR = 0;
#if defined MW_DEVBOARD_V2 || MW_DEBUG_UART
void debug_uart_tx_char(char c);
#pragma vector=USCI_A3_VECTOR
__interrupt void UCA_ISR (void)
{
switch (UCA3IV) {
case 2: // RXIFG
/* clear IRQ flag */
UCA3IFG &= ~UCRXIFG;
UART_RX_CHAR = UCA3RXBUF;
_event_src |= DBG_UART_RCV_EVENT;
/* wake up to handle the received char */
// LPM3_EXIT;
LPM3_EXIT_ISR();
break;
case 4: // TXIFG
break;
default:
break;
}
}
void init_debug_uart(void)
{
/* assert reset */
UCA3CTL1 = UCSWRST;
/* reset default SMCLK = 1.048MHz */
UCA3CTL1 |= UCSSEL__SMCLK;
/* CLK baud BRx BRSx BRFx */
/* 1,048,576 115200 9 1 0 */
/* 16,000,000 115200 138 7 0 */
UCA3BR0 = 138;
UCA3MCTL = UCBRS_7 | UCBRF_0;
/* set P10.4 & P10.5 to UCA function */
P10SEL |= BIT4;
P10SEL |= BIT5;
UCA3STAT = 0;
/* deassert reset */
UCA3CTL1 &= ~UCSWRST;
/* enable receive interrupt */
UCA3IE = UCRXIE;
/* clear interrup flags */
UCA3IFG = 0;
}
void debug_uart_tx_char(const char c)
{
while (UCA3STAT & UCBUSY)
nop();
UCA3TXBUF = c;
while ((UCA3IFG & UCTXIFG) == 0 )
nop();
}
void debug_uart_tx(const char *buf)
{
unsigned char i = 0;
while (buf[i] != 0) {
debug_uart_tx_char(buf[i]);
if (buf[i++] == '\n')
debug_uart_tx_char('\r');
}
while (UCA3STAT & UCBUSY)
nop();
}
void debug_dump_hex(const uint16_t len, const void *buf)
{
int i;
char tstr[8];
for (i=0; i<len; i++) {
snprintf(tstr, 8, "0x%02x ", *(uint8_t *)(buf+i));
debug_uart_tx(tstr);
}
debug_uart_tx("\n");
}
void debug_dump_ascii(const uint16_t len, const void *buf)
{
int i;
for (i=0; i<len; i++) {
debug_uart_tx_char(isprint(*(uint8_t *)(buf+i)) ? *(uint8_t *)(buf+i) : '.');
}
debug_uart_tx("\n");
}
char debug_uart_rx_char(char *c)
{
if (UART_RX_CHAR != 0) {
*c = UART_RX_CHAR;
UART_RX_CHAR = 0;
return 1;
} else {
*c = 0;
return 0;
}
}
#endif

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#ifndef _MW_UART_H
#define _MW_UART_H
#if defined MW_DEVBOARD_V2 || MW_DEBUG_UART
void init_debug_uart(void);
void debug_uart_tx_char(const char c);
void debug_uart_tx(const char *buf);
char debug_uart_rx_char(char *c);
void debug_dump_hex(const uint16_t len, const void *buf);
void debug_dump_ascii(const uint16_t len, const void *buf);
#else
#define debug_uart_tx(args...) {}
#define debug_uart_tx_char(args...) {}
#define debug_dump_hex(args...) {}
#define debug_dump_ascii(args...) {}
#endif
#endif

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/*
* Adaptation to Oswald
*/
#include <msp430.h>
#include <msp430xgeneric.h>
#include <stdint.h>
#include <string.h>
#include "mw_main.h"
#include "mw_lcd.h"
#include "mw_adc.h"
#include "mw_bt.h"
#include "bt_hci.h"
#include "bt_l2cap.h"
#include "bluetooth_init_cc256x.h"
#include "mw_acc.h"
#include "oswald.h"
#include "oswald_hal.h"
#include "calendar.h"
const char *hal_get_version_string(void)
{
return MW_MAIN_VERSION;
}
const char *hal_get_buildno_string(void)
{
return BUILDNO;
}
const char *hal_get_radio_version_string(void)
{
return cc256x_version;
}
void hal_lcd_set_pixel(uint8_t x, uint8_t y, uint8_t color)
{
if (x > 95)
x = 95;
if (y > 95)
y = 95;
mw_lcd_draw_pixel(x, y, color ? LCD_BLACK : LCD_WHITE);
}
void hal_lcd_clear_display(void)
{
mw_lcd_clear_fb();
}
void hal_lcd_update_display(void)
{
mw_lcd_update_screen();
}
void hal_lcd_set_backlight(boolean state)
{
if (state) {
ENABLE_LCD_LED();
} else {
DISABLE_LCD_LED();
}
}
boolean hal_lcd_get_backlight(void)
{
return (LCD_LED_POUT & LCD_LED_PIN) ? TRUE : FALSE;
}
void hal_enable_centisecond_timer(void)
{
start_timer(TIMER_100MS_CYCLES);
}
void hal_disable_centisecond_timer(void)
{
stop_timer();
}
void hal_enable_halfsecond_timer(void)
{
start_timer(TIMER_500MS_CYCLES);
}
void hal_disable_halfsecond_timer(void)
{
stop_timer();
}
void hal_get_rtc(clock_state *rtc)
{
/* Update clock state from RTC */
rtc->hour = RTCHOUR;
rtc->minute = RTCMIN;
rtc->second = RTCSEC;
rtc->day = RTCDAY;
rtc->month = RTCMON;
rtc->year = RTCYEAR;
rtc->wday = RTCDOW;
}
void hal_set_rtc(clock_state *rtc, boolean set_sec)
{
/* Update clock state from RTC */
RTCHOUR = rtc->hour;
RTCMIN = rtc->minute;
if (set_sec)
RTCSEC = rtc->second;
RTCDAY = rtc->day;
RTCMON = rtc->month;
RTCYEAR = rtc->year;
rtc->wday = getWochentag(rtc->day, rtc->month, rtc->year);
RTCDOW = rtc->wday;
}
void hal_get_power_state(power_state *pwr)
{
unsigned int val;
pwr->source = (BAT_CHARGE_IN & BAT_CHARGE_PWR_BIT) ? POWER_SOURCE_BATTERY : POWER_SOURCE_EXTERNAL;
/* unless the charger is enabled we do not get a reasonable state */
if (!(BAT_CHARGE_IN & BAT_CHARGE_ENABLE_PIN)) {
switch (BAT_CHARGE_IN & (BAT_CHARGE_STAT1 | BAT_CHARGE_STAT2)) {
case BAT_CHARGE_STAT1:
pwr->charge_state = POWER_CHARGER_DONE;
break;
case BAT_CHARGE_STAT2:
pwr->charge_state = POWER_CHARGER_CHARGING;
break;
case (BAT_CHARGE_STAT1 | BAT_CHARGE_STAT2):
pwr->charge_state = POWER_CHARGER_UNK;
break;
default:
pwr->charge_state = POWER_CHARGER_PRECHARGE;
break;
}
} else {
pwr->charge_state = POWER_CHARGER_UNK;
}
if ((pwr->source == POWER_SOURCE_BATTERY) && (RTCSEC != 0)) {
/* the ADC and activating the measuring shunts is
* power expensive so only do this every minute */
return;
};
/* get new values and so some averaging to avoid jumps */
val = mw_get_battery_adc_val();
pwr->percent = mw_get_battery_percentage_from_val(val);
pwr->level = val;
}
void hal_vibration_set_state(boolean state)
{
#ifdef MW_DIGITAL_V2
if (state) {
TA1CTL |= TASSEL__ACLK | MC__UPDOWN | ID_0;
P7SEL |= BIT3;
} else {
TA1CTL = 0;
P7SEL &= ~BIT3;
}
#endif
}
boolean hal_vibration_get_state(void)
{
#ifdef MW_DIGITAL_V2
return (P7SEL & BIT3) ? TRUE : FALSE;
#else
return FALSE;
#endif
}
#define BLUETOOTH_DEVICE_NAME "Oswald on MetaWatch"
static boolean bt_is_visible = FALSE;
bluetooth_state hal_bluetooth_set_state(bluetooth_state state)
{
uint8_t buf[32];
if (state == BLUETOOTH_OFF && mw_bt_is_enabled() == 1) {
mw_disable_bt();
bt_is_visible = FALSE;
return BLUETOOTH_OFF;
} else if (state == BLUETOOTH_ON && mw_bt_is_enabled() == 0) {
mw_enable_bt();
// set our name
memset(buf, 0, 32);
strncpy((char *)buf, BLUETOOTH_DEVICE_NAME, strlen(BLUETOOTH_DEVICE_NAME));
bt_hci_cmd(HCI_HC_BB_OGF, HCI_W_LOCAL_NAME_OCF, strlen(BLUETOOTH_DEVICE_NAME)+1, buf);
// read our local address
bt_hci_cmd(HCI_INFO_PARAM_OGF, HCI_R_BD_ADDR_OCF, 0, NULL);
// enable page scan
buf[0] = HCI_BB_SCAN_PAGE;
bt_hci_cmd(HCI_HC_BB_OGF, HCI_W_SCAN_EN_OCF, 1, buf);
bt_is_visible = FALSE;
return BLUETOOTH_ON;
} else
return BLUETOOTH_ILL;
}
bluetooth_state hal_bluetooth_get_state(void)
{
if (mw_bt_is_enabled() == 1) {
if (bt_l2cap_get_connected(0x40))
return BLUETOOTH_CONNECTED;
else
return BLUETOOTH_ON;
} else
return BLUETOOTH_OFF;
}
uint8_t *hal_bluetooth_get_local_bdaddr(void)
{
return bt_hci_get_local_bdaddr();
}
void hal_bluetooth_set_visible(boolean visible)
{
uint8_t buf[2];
if (mw_bt_is_enabled() == 0) {
bt_is_visible = FALSE;
return;
}
if (visible) {
// enable page and inquiry scan
buf[0] = HCI_BB_SCAN_INQUIRY | HCI_BB_SCAN_PAGE;
bt_hci_cmd(HCI_HC_BB_OGF, HCI_W_SCAN_EN_OCF, 1, buf);
bt_is_visible = TRUE;
} else {
// enable page scan only
buf[0] = HCI_BB_SCAN_PAGE;
bt_hci_cmd(HCI_HC_BB_OGF, HCI_W_SCAN_EN_OCF, 1, buf);
bt_is_visible = FALSE;
}
}
boolean hal_bluetooth_get_visible(void)
{
return bt_is_visible;
}
void hal_bluetooth_send_data(const void *mdat, uint16_t mlen)
{
bt_l2cap_send_channel(0x40, mdat, mlen);
}
/*
* Control the accelerometer
*/
void hal_accelerometer_enable(void)
{
mw_acc_enable();
}
void hal_accelerometer_disable(void)
{
mw_acc_disable();
}
uint16_t hal_amblight_get_val(void)
{
return mw_get_amblight_adc_val();
}

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metawatch/sharp_mem_lcd.c Normal file
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// taken and adapted from
// Programming Sharps Memory LCDs
// by Ken Green
// LCD commands - Note: the bits are reversed per the memory LCD data
// sheets because of the order the bits are shifted out in the SPI
// port.
#define MLCD_WR 0x80 //MLCD write line command
#define MLCD_CM 0x20 //MLCD clear memory command
#define MLCD_NO 0x00 //MLCD NOP command (used to switch VCOM)
//LCD resolution
#define MLCD_XRES 96 //pixels per horizontal line
#define MLCD_YRES 96 //pixels per vertical line
#define MLCD_BYTES_LINE MLCD_XRES / 8 //number of bytes in a line
#define MLCD_BUF_SIZE MLCD_YRES * MLCD_BYTES_LINE
//defines the VCOM bit in the command word that goes to the LCD
#define VCOM_HI 0x40
#define VCOM_LO 0x00
static char *frmbufter; //current address of buffer to be displayed
static char locbuf[MLCD_BYTES_LINE + 3]; // local line buffer
static char linenum; // current line number being transmitted
//there are 3 stages in transmitting a buffer:
//stage 0: first line (has command in it)
//stage 1: 2nd through last line (no command)
//stage 2: null byte trailer
static int stage = 0;
//current state of vcom. This should alternate
//between VCOM _ HI and VCOM _ LO on a 1-30 second
//period.
extern char vcom;
////////////////////////////////////////////////////////////////
//
// This routine transmits the contents of the pixel memory in
// a frame buffer to the memory LCD. It uses DMA to transfer
// each individual line. The address of the frame buffer to
// transfer is in the global variable show _ frm.
//
//
// NOTE: this routine also acts as the interrupt handler for SPI interrupts.
//
//
// INPUTS:
// The SPI and DMA units must have been previously initialized
// show _ frm:
// pointer to the buffer to be displayed
//
////////////////////////////////////////////////////////////////
void show _ frame(char *show _ frm) {
int i;
unsigned long sts;
switch(stage) {
case 0:
// stage 0: sending the first line. The command is
// included in this line
set_scs(HIGH); //set SCS high
frmbufptr = show_frm; //init pointer to frame buffer
linebuf = locbuf; //init pointer to line buffer
linenum = 1; //init line address
//first line of data is preceeded by a write command
*linebuf++ = MLCD _ WR | vcom; //command (note: no need to swap)
*linebuf++ = swap(linenum++); //line number (address)
for (i=0; i<MLCD_BYTES_LINE; i++)
*linebuf++ = swap(*frmbufptr++); //swap the order of the bits
*linebuf++ = 0; //trailer
//Setup the SPI DMA controller (starting addr, size)
TransferSetup(locbuf, linebuf - locbuf);
//Start the xfer
TransferStart;
stage = 1; //set to next stage
break;
case 1: //Sending a line (other than the first line). At this
//point the DMA transfer for the previous line is done
//and the channel disabled.
linebuf = locbuf; //init pointer to line buffer
*linebuf++ = swap(linenum++); //line number
for (i=0; i<MLCD_BYTES_LINE; i++)
*linebuf++ = swap(*frmbufptr++); //swap the order of the bits
*linebuf++ = 0; //trailer
//set up DMA control
TransferSetup(locbuf, linebuf - locbuf);
//Start the xfer
TransferStart;
if (linenum > MLCD_YRES)
stage = 2; //all lines sent, go to next stage
break;
case 2:
// All lines sent, send a fi nal null byte trailer. The DMA
//transfer of the last line is fi nished and the channel
//disabled. All that is left is to write a trailing null
//byte. Its not worth using DMA to transfer 1 byte, so
//its done by directing writing to the SPI port.
//Write the last (null) byte
Write_to_SPI(0);
//Since there is no interrupt on transmit buffer empty, loop
//here until the byte is sent, then drop SCS.
i = 0;
while (SPI_BSY); //wait until done
set_scs(LOW);
stage = 0; //go back to stage 0 - sending out first line
}
}

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metawatch/sintab.py Normal file
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import sys
import math
sys.stdout.write ("int16_t sintab[]={ ")
for i in range (0, 360):
sys.stdout.write ("%4.0f," % (math.sin(((2*3.14159265358979323846)/360)*i)*100))
sys.stdout.write ("};\n")

23
ui/Makefile.am Normal file
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ACLOCAL_AMFLAGS = -I m4
bin_PROGRAMS = .buildno oswald-gui
oswald_gui_SOURCES = oswald-ui.c oswald_main.c \
oswald_watch_faces.c oswald_strings.c oswald_screens.c \
embedvm.c oswald_graphics.c calendar.c oswald_fonts.c
# BUILDNO = \"$(shell cat .buildno)\"
BUILDNO = \"$(shell date +%y%m%d)-\#$(shell cat .buildno)\"
oswald_gui_CFLAGS = -DBUILDNO=$(BUILDNO) -g $(GTK_CFLAGS)
oswald_gui_LDADD = $(GTK_LIBS)
EXTRA_DIST = config.rpath m4/ChangeLog \
AUTHORS \
COPYING \
README.txt
.buildno: $(oswald_gui_OBJECTS)
@if ! test -f .buildno; then echo 0 > .buildno; fi
@echo $$(($$(cat .buildno) + 1)) > .buildno

8
ui/autogen.sh Executable file
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#!/bin/sh
version=1.11
set -x
aclocal-$version
autoconf
libtoolize
automake-$version --add-missing --foreign

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#define Bluetooth_icon_width 24
#define Bluetooth_icon_height 24
static unsigned char Bluetooth_icon_bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x38, 0x00,
0x00, 0x78, 0x00, 0x00, 0xd8, 0x00, 0x80, 0x98, 0x01, 0x80, 0x19, 0x03,
0x00, 0x9b, 0x01, 0x00, 0xde, 0x00, 0x00, 0x7c, 0x00, 0x00, 0x38, 0x00,
0x00, 0x3c, 0x00, 0x00, 0x7e, 0x00, 0x00, 0xdb, 0x00, 0x80, 0x99, 0x01,
0x80, 0x18, 0x03, 0x00, 0x98, 0x01, 0x00, 0xd8, 0x00, 0x00, 0x78, 0x00,
0x00, 0x38, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
};

10
ui/bitmaps/Exit_icon.xbm Normal file
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#define Exit_icon_width 24
#define Exit_icon_height 24
static unsigned char Exit_icon_bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 0xf0, 0xff, 0x03,
0x30, 0x0c, 0x03, 0x30, 0x0c, 0x03, 0x30, 0x0c, 0x03, 0x30, 0x0c, 0x01,
0x30, 0x0c, 0x02, 0x30, 0x0c, 0x03, 0x30, 0x8c, 0x03, 0x30, 0xcc, 0x1f,
0x30, 0xcc, 0x1f, 0x30, 0x8c, 0x03, 0x30, 0x0c, 0x03, 0x30, 0x06, 0x02,
0x30, 0x03, 0x01, 0xb0, 0x01, 0x03, 0xf0, 0x00, 0x03, 0x70, 0x00, 0x03,
0xf0, 0xff, 0x03, 0xf0, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
};

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#define Message_icon_width 24
#define Message_icon_height 24
static unsigned char Message_icon_bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x3f,
0xfc, 0xff, 0x3f, 0x3c, 0x00, 0x3c, 0x6c, 0x00, 0x36, 0xcc, 0x00, 0x33,
0x8c, 0x81, 0x31, 0x0c, 0xc3, 0x30, 0x0c, 0x66, 0x30, 0x0c, 0x3c, 0x30,
0x0c, 0x18, 0x30, 0x0c, 0x00, 0x30, 0x0c, 0x00, 0x30, 0x0c, 0x00, 0x30,
0x0c, 0x00, 0x30, 0x0c, 0x00, 0x30, 0xfc, 0xff, 0x3f, 0xfc, 0xff, 0x3f,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
};

10
ui/bitmaps/acc_icon.xbm Normal file
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#define acc_icon_width 24
#define acc_icon_height 24
static unsigned char acc_icon_bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x00, 0x00, 0x20, 0x00, 0x00,
0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x70, 0x00, 0x00,
0xa8, 0xe0, 0x00, 0x20, 0x40, 0x00, 0x20, 0xe0, 0x00, 0x20, 0x0e, 0x00,
0x20, 0x0c, 0x00, 0x20, 0x0a, 0x00, 0x20, 0x01, 0x00, 0xa0, 0x40, 0x00,
0x60, 0x80, 0x14, 0xf8, 0xff, 0x09, 0x30, 0x80, 0x14, 0x28, 0x40, 0x00,
0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
};

10
ui/bitmaps/alarm_icon.xbm Normal file
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#define alarm_icon_width 24
#define alarm_icon_height 24
static unsigned char alarm_icon_bits[] = {
0x00, 0x00, 0x00, 0x1c, 0x00, 0x38, 0x1e, 0xff, 0x78, 0xce, 0xff, 0x73,
0xe6, 0x00, 0x67, 0x70, 0x18, 0x0e, 0x38, 0x18, 0x1c, 0x18, 0x18, 0x18,
0x0c, 0x18, 0x30, 0x0c, 0x18, 0x30, 0x0c, 0x18, 0x30, 0x0c, 0xf8, 0x31,
0x0c, 0xf8, 0x31, 0x0c, 0x00, 0x30, 0x0c, 0x00, 0x30, 0x0c, 0x00, 0x30,
0x18, 0x00, 0x18, 0x38, 0x00, 0x1c, 0x70, 0x00, 0x0e, 0xe0, 0x00, 0x07,
0xc0, 0xff, 0x03, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
};

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#define battery0_icon_width 15
#define battery0_icon_height 20
static unsigned char battery0_icon_bits[] = {
0x00, 0x00, 0x00, 0x1c, 0x00, 0x3e, 0x00, 0x22, 0x00, 0x22, 0x00, 0x22,
0x00, 0x22, 0x00, 0x22, 0x00, 0x22, 0x00, 0x22, 0x00, 0x22, 0x00, 0x22,
0x00, 0x22, 0x00, 0x22, 0x00, 0x22, 0x00, 0x22, 0x00, 0x22, 0x00, 0x3e,
0x00, 0x00, 0x00, 0x00, };

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#define battery100_icon_width 15
#define battery100_icon_height 20
static unsigned char battery100_icon_bits[] = {
0x00, 0x00, 0x00, 0x1c, 0x00, 0x3e, 0x00, 0x3e, 0x00, 0x3e, 0x00, 0x3e,
0x00, 0x3e, 0x00, 0x3e, 0x00, 0x3e, 0x00, 0x3e, 0x00, 0x3e, 0x00, 0x3e,
0x00, 0x3e, 0x00, 0x3e, 0x00, 0x3e, 0x00, 0x3e, 0x00, 0x3e, 0x00, 0x3e,
0x00, 0x00, 0x00, 0x00, };

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#define battery25_icon_width 15
#define battery25_icon_height 20
static unsigned char battery25_icon_bits[] = {
0x00, 0x00, 0x00, 0x1c, 0x00, 0x3e, 0x00, 0x22, 0x00, 0x22, 0x00, 0x22,
0x00, 0x22, 0x00, 0x22, 0x00, 0x22, 0x00, 0x22, 0x00, 0x22, 0x00, 0x22,
0x00, 0x22, 0x00, 0x3e, 0x00, 0x3e, 0x00, 0x3e, 0x00, 0x3e, 0x00, 0x3e,
0x00, 0x00, 0x00, 0x00, };

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#define battery50_icon_width 15
#define battery50_icon_height 20
static unsigned char battery50_icon_bits[] = {
0x00, 0x00, 0x00, 0x1c, 0x00, 0x3e, 0x00, 0x22, 0x00, 0x22, 0x00, 0x22,
0x00, 0x22, 0x00, 0x22, 0x00, 0x22, 0x00, 0x3e, 0x00, 0x3e, 0x00, 0x3e,
0x00, 0x3e, 0x00, 0x3e, 0x00, 0x3e, 0x00, 0x3e, 0x00, 0x3e, 0x00, 0x3e,
0x00, 0x00, 0x00, 0x00, };

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#define battery75_icon_width 15
#define battery75_icon_height 20
static unsigned char battery75_icon_bits[] = {
0x00, 0x00, 0x00, 0x1c, 0x00, 0x3e, 0x00, 0x22, 0x00, 0x22, 0x00, 0x3e,
0x00, 0x3e, 0x00, 0x3e, 0x00, 0x3e, 0x00, 0x3e, 0x00, 0x3e, 0x00, 0x3e,
0x00, 0x3e, 0x00, 0x3e, 0x00, 0x3e, 0x00, 0x3e, 0x00, 0x3e, 0x00, 0x3e,
0x00, 0x00, 0x00, 0x00, };

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#define bluetooth_con_icon_width 15
#define bluetooth_con_icon_height 20
static unsigned char bluetooth_con_icon_bits[] = {
0x6c, 0x00, 0xce, 0x00, 0xaa, 0x00, 0xc6, 0x00, 0xaa, 0x00, 0xce, 0x00,
0x6c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, };

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#define bluetooth_icon_width 15
#define bluetooth_icon_height 20
static unsigned char bluetooth_icon_bits[] = {
0x10, 0x00, 0x30, 0x00, 0x54, 0x00, 0x38, 0x00, 0x54, 0x00, 0x30, 0x00,
0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, };

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#define charger_icon_width 15
#define charger_icon_height 20
static unsigned char charger_icon_bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x7c, 0x00,
0x7c, 0x00, 0x38, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00,
0x00, 0x00, 0x00, 0x00, };

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#define checked_icon_width 7
#define checked_icon_height 7
static unsigned char checked_icon_bits[] = {
0x7f, 0x41, 0x5d, 0x5d, 0x5d, 0x41, 0x7f, };

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#define downbutton_icon_width 15
#define downbutton_icon_height 20
static unsigned char downbutton_icon_bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c,
0x00, 0x0c, 0x00, 0x0c, 0x00, 0x0c, 0x00, 0x0c, 0x80, 0x7f, 0x00, 0x3f,
0x00, 0x1e, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, };

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#define enterbutton_icon_width 15
#define enterbutton_icon_height 20
static unsigned char enterbutton_icon_bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x64, 0x00, 0x66, 0x00, 0x67, 0x80, 0x7f, 0x80, 0x7f, 0x00, 0x07,
0x00, 0x06, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, };

10
ui/bitmaps/exit_icon.xbm Normal file
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#define exit_icon_width 24
#define exit_icon_height 24
static unsigned char exit_icon_bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 0xf0, 0xff, 0x03,
0x30, 0x0c, 0x03, 0x30, 0x0c, 0x03, 0x30, 0x0c, 0x03, 0x30, 0x0c, 0x01,
0x30, 0x0c, 0x02, 0x30, 0x0c, 0x03, 0x30, 0x8c, 0x03, 0x30, 0xcc, 0x1f,
0x30, 0xcc, 0x1f, 0x30, 0x8c, 0x03, 0x30, 0x0c, 0x03, 0x30, 0x06, 0x02,
0x30, 0x03, 0x01, 0xb0, 0x01, 0x03, 0xf0, 0x00, 0x03, 0x70, 0x00, 0x03,
0xf0, 0xff, 0x03, 0xf0, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
};

10
ui/bitmaps/info_icon.xbm Normal file
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#define info_icon_width 24
#define info_icon_height 24
static unsigned char info_icon_bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0xc0, 0xff, 0x03,
0xe0, 0x00, 0x07, 0x70, 0x1c, 0x0e, 0x38, 0x1c, 0x1c, 0x18, 0x1c, 0x18,
0x0c, 0x00, 0x30, 0x0c, 0x1c, 0x30, 0x0c, 0x1c, 0x30, 0x0c, 0x1c, 0x30,
0x0c, 0x1c, 0x30, 0x0c, 0x1c, 0x30, 0x0c, 0x1c, 0x30, 0x0c, 0x1c, 0x30,
0x18, 0x1c, 0x18, 0x38, 0x1c, 0x1c, 0x70, 0x00, 0x0e, 0xe0, 0x00, 0x07,
0xc0, 0xff, 0x03, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
};

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#define lapsebutton_icon_width 15
#define lapsebutton_icon_height 20
static unsigned char lapsebutton_icon_bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x61,
0x00, 0x63, 0x00, 0x67, 0xc0, 0x6f, 0xc0, 0x6f, 0x00, 0x67, 0x00, 0x63,
0x00, 0x61, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, };

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#define leftbutton_icon_width 15
#define leftbutton_icon_height 20
static unsigned char leftbutton_icon_bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x04, 0x00, 0x06, 0x00, 0x07, 0x80, 0x7f, 0x80, 0x7f, 0x00, 0x07,
0x00, 0x06, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, };

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#define main_menu_icon_width 24
#define main_menu_icon_height 24
static unsigned char main_menu_icon_bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x1f, 0xfc, 0xff, 0x3f,
0x0c, 0x00, 0x30, 0x0c, 0x00, 0x30, 0x0c, 0x00, 0x30, 0x0c, 0x00, 0x30,
0xcc, 0xdd, 0x31, 0xcc, 0xdd, 0x31, 0xcc, 0xdd, 0x31, 0x0c, 0x00, 0x30,
0xcc, 0xdd, 0x31, 0xcc, 0xdd, 0x31, 0xcc, 0xdd, 0x31, 0x0c, 0x00, 0x30,
0x0c, 0x00, 0x30, 0x0c, 0x00, 0x30, 0x0c, 0x00, 0x30, 0xfc, 0xff, 0x3f,
0xf8, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
};

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#define message_icon_width 24
#define message_icon_height 24
static unsigned char message_icon_bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0xfe, 0xff, 0x7f, 0xfe, 0xff, 0x7f, 0x0e, 0x00, 0x70,
0x1e, 0x00, 0x78, 0x36, 0x00, 0x6c, 0x66, 0x00, 0x66, 0xc6, 0x00, 0x63,
0x86, 0x81, 0x61, 0x06, 0xc3, 0x60, 0x06, 0x66, 0x60, 0x06, 0x3c, 0x60,
0x06, 0x18, 0x60, 0x06, 0x00, 0x60, 0x06, 0x00, 0x60, 0x06, 0x00, 0x60,
0xfe, 0xff, 0x7f, 0xfe, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
};

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#define resetbutton_icon_width 15
#define resetbutton_icon_height 20
static unsigned char resetbutton_icon_bits[] = {
0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x0c, 0x00, 0x0e, 0x00, 0xff, 0x00,
0xff, 0x00, 0xce, 0x00, 0xcc, 0x00, 0xc8, 0x00, 0xc0, 0x00, 0xc0, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, };

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#define rightbutton_icon_width 15
#define rightbutton_icon_height 20
static unsigned char rightbutton_icon_bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x08, 0x00, 0x18, 0x00, 0x38, 0x80, 0x7f, 0x80, 0x7f, 0x00, 0x38,
0x00, 0x18, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, };

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#define startstopbutton_icon_width 15
#define startstopbutton_icon_height 20
static unsigned char startstopbutton_icon_bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b,
0x00, 0x1b, 0x00, 0x3b, 0x00, 0x7b, 0x00, 0x7b, 0x00, 0x3b, 0x00, 0x1b,
0x00, 0x0b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, };

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#define stopwatch_width 24
#define stopwatch_height 24
static unsigned char stopwatch_bits[] = {
0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x18, 0x00, 0x00, 0x18, 0x00,
0x00, 0x7e, 0x10, 0x80, 0x81, 0x39, 0x40, 0x18, 0x1e, 0x20, 0x18, 0x0c,
0x10, 0x18, 0x08, 0x08, 0x18, 0x10, 0x08, 0x18, 0x10, 0x04, 0x18, 0x20,
0x04, 0x18, 0x20, 0x04, 0x18, 0x20, 0x04, 0x00, 0x20, 0x04, 0x00, 0x20,
0x04, 0x00, 0x20, 0x08, 0x00, 0x10, 0x08, 0x00, 0x10, 0x10, 0x00, 0x08,
0x20, 0x00, 0x04, 0x40, 0x00, 0x02, 0x80, 0x81, 0x01, 0x00, 0x7e, 0x00,
};

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#define stopwatch_icon_width 24
#define stopwatch_icon_height 24
static unsigned char stopwatch_icon_bits[] = {
0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x3c, 0x00, 0x00, 0xff, 0x0c,
0xc0, 0xff, 0x1f, 0xe0, 0x00, 0x1f, 0x70, 0x18, 0x0e, 0x38, 0x18, 0x1c,
0x18, 0x18, 0x18, 0x0c, 0x18, 0x30, 0x0c, 0x18, 0x30, 0x0c, 0x18, 0x30,
0x0c, 0x18, 0x30, 0x0c, 0x18, 0x30, 0x0c, 0x00, 0x30, 0x0c, 0x00, 0x30,
0x0c, 0x00, 0x30, 0x18, 0x00, 0x18, 0x38, 0x00, 0x1c, 0x70, 0x00, 0x0e,
0xe0, 0x00, 0x07, 0xc0, 0xff, 0x03, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00,
};

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#define timesetup_icon_width 24
#define timesetup_icon_height 24
static unsigned char timesetup_icon_bits[] = {
0x00, 0xff, 0x00, 0xc0, 0xff, 0x03, 0xe0, 0x00, 0x07, 0x70, 0x18, 0x0e,
0x38, 0x18, 0x1c, 0x18, 0x18, 0x18, 0x0c, 0x18, 0x30, 0x0c, 0x18, 0x30,
0x0c, 0x18, 0x30, 0x0c, 0xf8, 0x31, 0x0c, 0xf8, 0x31, 0x0c, 0x00, 0x30,
0x0c, 0x00, 0x30, 0x0c, 0x00, 0x30, 0x18, 0x00, 0x18, 0x38, 0x00, 0x1c,
0x70, 0x00, 0x0e, 0xe0, 0x00, 0x07, 0xc0, 0xff, 0x03, 0x00, 0xff, 0x00,
0xfe, 0x00, 0x00, 0xff, 0xff, 0x3f, 0xff, 0xff, 0x3f, 0xfe, 0x00, 0x00,
};

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#define unchecked_icon_width 7
#define unchecked_icon_height 7
static unsigned char unchecked_icon_bits[] = {
0x7f, 0x41, 0x41, 0x41, 0x41, 0x41, 0x7f, };

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#define upbutton_icon_width 15
#define upbutton_icon_height 20
static unsigned char upbutton_icon_bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c,
0x00, 0x1e, 0x00, 0x3f, 0x80, 0x7f, 0x00, 0x0c, 0x00, 0x0c, 0x00, 0x0c,
0x00, 0x0c, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, };

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#define watch_icon_width 24
#define watch_icon_height 24
static unsigned char watch_icon_bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0xff, 0x00, 0xc0, 0xff, 0x03, 0xe0, 0x00, 0x07, 0x70, 0x18, 0x0e,
0x38, 0x18, 0x1c, 0x18, 0x18, 0x18, 0x0c, 0x18, 0x30, 0x0c, 0x18, 0x30,
0x0c, 0x18, 0x30, 0x0c, 0xf8, 0x31, 0x0c, 0xf8, 0x31, 0x0c, 0x00, 0x30,
0x0c, 0x00, 0x30, 0x0c, 0x00, 0x30, 0x18, 0x00, 0x18, 0x38, 0x00, 0x1c,
0x70, 0x00, 0x0e, 0xe0, 0x00, 0x07, 0xc0, 0xff, 0x03, 0x00, 0xff, 0x00,
};

209
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#include "oswald.h"
#include "calendar.h"
unsigned char is_leap(const unsigned int year)
{
/* the rule is, everything that can be devided by 4 is leap.
* Exception: the year can be devided by 100, then it is not,
* except it canbe devided by 400, then it is again.
*/
if ((year % 400) == 0)
return 1;
else if ((year % 100) == 0)
return 0;
else if ((year % 4) == 0)
return 1;
return 0;
}
unsigned short days_of_month(const unsigned int uMonat, const unsigned int uJahr)
{
// invalid,January,Febuary,March,April,May,June,July,August,September,October,November,December
int arrTageImMonat[13] = { 0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };
if (uMonat == 2) {
// Febuary: distinguish leap
if (is_leap(uJahr))
return 29;
else
return 28;
}
if ((uMonat >= 1) && (uMonat <= 12))
return arrTageImMonat[uMonat];
else {
return 0;
}
}
short getAnzahlTageImJahr(const unsigned int uJahr)
{
return (is_leap(uJahr)) ? 366 : 365;
}
short getWochentag(const unsigned int uTag, const unsigned int uMonat, const unsigned int uJahr)
{
// ungült Jan Feb Mrz Apr Mai Jun Jul Aug Sep Okt Nov Dez
unsigned char arrMonatsOffset[13] = { 0, 0, 3, 3, 6, 1, 4, 6, 2, 5, 0, 3, 5};
short nErgebnis = 0;
// Monat / Tag - Plausi prüfen:
if ((uTag > 31) || (uMonat > 12) || (uMonat <= 0)
|| (uTag <= 0) || (uJahr <= 0)) {
return -1;
}
unsigned char cbTagesziffer = (uTag % 7);
unsigned char cbMonatsziffer = arrMonatsOffset[uMonat];
unsigned char cbJahresziffer = ((uJahr % 100) + ((uJahr % 100) / 4)) % 7;
unsigned char cbJahrhundertziffer = (3 - ((uJahr / 100) % 4)) * 2;
// Schaltjahreskorrektur:
if ((uMonat <= 2) && (is_leap(uJahr)))
cbTagesziffer = cbTagesziffer + 6;
nErgebnis = (cbTagesziffer + cbMonatsziffer + cbJahresziffer + cbJahrhundertziffer) % 7;
// Ergebnis:
// 0 = Sonntag
// 1 = Montag
// 2 = Dienstag
// 3 = Mittwoch
// 4 = Donnerstag
// 5 = Freitag
// 6 = Samstag
return nErgebnis;
}
short getTagDesJahres(const unsigned int uTag, const unsigned int uMonat, const unsigned int uJahr)
{
// Der wievielte Tag des Jahres ist dieser Tag
if ((uMonat == 0) || (uMonat > 12)) {
return -1;
}
unsigned int uLokalTag = uTag;
unsigned int uLokalMonat = uMonat;
while (uLokalMonat > 1) {
uLokalMonat--;
uLokalTag += days_of_month(uLokalMonat, uJahr);
}
return uLokalTag;
}
short getKalenderwoche(short uTag, short uMonat, short uJahr)
{
// Berechnung erfolgt analog DIN 1355, welche besagt:
// Der erste Donnerstag im neuen Jahr liegt immer in der KW 1.
// "Woche" ist dabei definiert als [Mo, ..., So].
short nTagDesJahres = getTagDesJahres(uTag, uMonat, uJahr);
// Berechnen des Wochentags des 1. Januar:
short nWochentag1Jan = getWochentag(1, 1, uJahr);
// Sonderfälle Freitag und Samstag
if (nWochentag1Jan >= 5)
nWochentag1Jan = nWochentag1Jan - 7;
// Sonderfälle "Jahresanfang mit KW - Nummer aus dem Vorjahr"
if ( (nTagDesJahres + nWochentag1Jan) <= 1) {
return getKalenderwoche(31, 12, uJahr - 1);
}
short nKalenderWoche = ((nTagDesJahres + nWochentag1Jan + 5) / 7);
// 53 Kalenderwochen hat grundsätzlich nur ein Jahr,
// welches mit einem Donnerstag anfängt !
// In Schaltjahren ist es auch mit einem Mittwoch möglich, z.B. 1992
// Andernfalls ist diese KW schon die KW1 des Folgejahres.
if (nKalenderWoche == 53) {
boolean bIstSchaltjahr = is_leap(uJahr);
if ((nWochentag1Jan == 4) // Donnerstag
|| (nWochentag1Jan == -3) // auch Donnerstag
|| ((nWochentag1Jan == 3) && bIstSchaltjahr)
|| ((nWochentag1Jan == -4) && bIstSchaltjahr)) {
; // Das ist korrekt und erlaubt
} else
nKalenderWoche = 1; // Korrektur des Wertes
}
return nKalenderWoche;
}
void getOsterdatum(const unsigned int uJahr, unsigned int *uTag, unsigned int *uMonat)
{
// Berechnet für ein beliebiges Jahr das Osterdatum.
// Quelle des Gauss - Algorithmus: Stefan Gerth,
// "Die Gauß'sche Osterregel", Nürnberg, Februar 2003.
// http://krapfen.org/content/paper/Schule/Facharbeit/Berechnung_des_Osterfestes.pdf
unsigned int a = uJahr % 19;
unsigned int b = uJahr % 4;
unsigned int c = uJahr % 7;
int k = uJahr / 100;
int q = k / 4;
int p = ((8 * k) + 13) / 25;
unsigned int Egz = (38 - (k - q) + p) % 30; // Die Jahrhundertepakte
unsigned int M = (53 - Egz) % 30;
unsigned int N = (4 + k - q) % 7;
unsigned int d = ((19 * a) + M) % 30;
unsigned int e = ((2 * b) + (4 * c) + (6 * d) + N) % 7;
// Ausrechnen des Ostertermins:
if ((22 + d + e) <= 31) {
*uTag = 22 + d + e;
*uMonat = 3;
} else {
*uTag = d + e - 9;
*uMonat = 4;
// Zwei Ausnahmen berücksichtigen:
if (*uTag == 26)
*uTag = 19;
else if ((*uTag == 25) && (d == 28) && (a > 10))
*uTag = 18;
}
// Offsets für andere Feiertage:
// Schwerdonnerstag / Weiberfastnacht -52
// Rosenmontag -48
// Fastnachtsdienstag -47
// Aschermittwoch -46
// Gründonnerstag -3
// Karfreitag -2
// Ostersonntag 0
// Ostermontag +1
// Christi Himmelfahrt +39
// Pfingstsonntag +49
// Pfingstmontag +50
// Fronleichnam +60
// Mariä Himmelfahrt ist stets am 15. August (Danke an Michael Plugge!)
}
void getViertenAdvent(const unsigned int uJahr, unsigned int *uTag, unsigned int *uMonat)
{
// Berechnet für ein beliebiges Jahr das Datum des 4. Advents-Sonntags.
// Der 4. Adventssonntag ist stets der Sonntag vor dem 1. Weihnachtsfeiertag,
// muß also stets in der Periode [18. - 24.12.] liegen:
*uMonat = 12; // Das steht jedes Jahr fest :-)
short nWoTag = getWochentag(24, 12, uJahr); // Wochentag des 24.12. ermitteln
*uTag = 24 - nWoTag;
// Offsets: Der Buß- und Bettag liegt stets 32 Tage vor dem 4. Advent
}

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#ifndef _CALENDAR_H
#define _CALENDAR_H
unsigned char is_leap(const unsigned int year);
unsigned short days_of_month(const unsigned int uMonat, const unsigned int uJahr);
short getAnzahlTageImJahr(const unsigned int uJahr);
short getWochentag(const unsigned int uTag, const unsigned int uMonat, const unsigned int uJahr);
short getTagDesJahres(const unsigned int uTag, const unsigned int uMonat, const unsigned int uJahr);
short getKalenderwoche(short uTag, short uMonat, short uJahr);
void getOsterdatum(const unsigned int uJahr, unsigned int *uTag, unsigned int *uMonat);
void getViertenAdvent(const unsigned int uJahr, unsigned int *uTag, unsigned int *uMonat);
#endif

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AC_CONFIG_MACRO_DIR([m4])
# AC_CONFIG_HEADER(config.h)
AC_INIT(Makefile.am)
AM_INIT_AUTOMAKE(oswald-gui, 0.01)
AC_PROG_CPP
AC_PROG_INSTALL
AC_PROG_LIBTOOL
AM_MAINTAINER_MODE
PKG_CHECK_MODULES(GTK, gtk+-2.0)
AC_SUBST(GTK_LIBS)
AC_SUBST(GTK_CFLAGS)
AC_OUTPUT([ Makefile ])

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/*
* EmbedVM - Embedded Virtual Machine for uC Applications
*
* Copyright (C) 2011 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "embedvm.h"
static inline int16_t signext(uint16_t val, uint16_t mask)
{
val = val & mask;
if ((val & ~(mask >> 1)) != 0)
val |= ~mask;
return val;
}
extern void embedvm_exec(struct embedvm_s *vm)
{
uint8_t opcode = vm->mem_read(vm->ip, false, vm->user_ctx);
uint16_t addr = 0;
int16_t a = 0, b = 0;
int8_t sfa = 0;
switch (opcode)
{
case 0x00 ... 0x3f:
sfa = signext(opcode, 0x3f);
embedvm_push(vm, embedvm_local_read(vm, sfa));
vm->ip++;
break;
case 0x40 ... 0x7f:
sfa = signext(opcode, 0x3f);
embedvm_local_write(vm, sfa, embedvm_pop(vm));
vm->ip++;
break;
case 0x80+0 ... 0x80+11:
case 0xa8+0 ... 0xa8+5:
b = embedvm_pop(vm);
case 0x80+12 ... 0x80+14:
a = embedvm_pop(vm);
switch (opcode)
{
case 0x80 + 0: embedvm_push(vm, a + b); break;
case 0x80 + 1: embedvm_push(vm, a - b); break;
case 0x80 + 2: embedvm_push(vm, a * b); break;
case 0x80 + 3: embedvm_push(vm, a / b); break;
case 0x80 + 4: embedvm_push(vm, a % b); break;
case 0x80 + 5: embedvm_push(vm, a << b); break;
case 0x80 + 6: embedvm_push(vm, a >> b); break;
case 0x80 + 7: embedvm_push(vm, a & b); break;
case 0x80 + 8: embedvm_push(vm, a | b); break;
case 0x80 + 9: embedvm_push(vm, a ^ b); break;
case 0x80 + 10: embedvm_push(vm, a && b); break;
case 0x80 + 11: embedvm_push(vm, a || b); break;
case 0x80 + 12: embedvm_push(vm, ~a); break;
case 0x80 + 13: embedvm_push(vm, -a); break;
case 0x80 + 14: embedvm_push(vm, !a); break;
case 0xa8 + 0: embedvm_push(vm, a < b); break;
case 0xa8 + 1: embedvm_push(vm, a <= b); break;
case 0xa8 + 2: embedvm_push(vm, a == b); break;
case 0xa8 + 3: embedvm_push(vm, a != b); break;
case 0xa8 + 4: embedvm_push(vm, a >= b); break;
case 0xa8 + 5: embedvm_push(vm, a > b); break;
}
vm->ip++;
break;
case 0x90 ... 0x97:
a = signext(opcode, 0x07);
if ((a & 0x04) != 0)
a |= ~0x07;
embedvm_push(vm, a);
vm->ip++;
break;
case 0x98:
a = vm->mem_read(vm->ip+1, false, vm->user_ctx) & 0x00ff;
embedvm_push(vm, a);
vm->ip += 2;
break;
case 0x99:
a = vm->mem_read(vm->ip+1, false, vm->user_ctx) & 0x00ff;
embedvm_push(vm, signext(a, 0x00ff));
vm->ip += 2;
break;
case 0x9a:
a = vm->mem_read(vm->ip+1, true, vm->user_ctx);
embedvm_push(vm, a);
vm->ip += 3;
break;
case 0x9b:
a = embedvm_pop(vm);
if (0) {
case 0x9c:
a = 0;
}
vm->sp = vm->sfp;
vm->ip = embedvm_pop(vm);
vm->sfp = embedvm_pop(vm);
if ((vm->sfp & 1) != 0)
vm->sfp &= ~1;
else
embedvm_push(vm, a);
break;
case 0x9d:
embedvm_pop(vm);
vm->ip++;
break;
case 0x9e:
addr = embedvm_pop(vm);
if (vm->mem_read(vm->ip+1, false, vm->user_ctx) == 0x9d) {
embedvm_push(vm, vm->sfp | 1);
embedvm_push(vm, vm->ip + 2);
} else {
embedvm_push(vm, vm->sfp);
embedvm_push(vm, vm->ip + 1);
}
vm->sfp = vm->sp;
vm->ip = addr;
break;
case 0x9f:
vm->ip = embedvm_pop(vm);
break;
case 0xa0 ... 0xa0+7:
if ((opcode & 1) == 0) {
addr = vm->ip + signext(vm->mem_read(vm->ip+1, false, vm->user_ctx), 0x00ff);
vm->ip += 2;
} else {
addr = vm->ip + vm->mem_read(vm->ip+1, true, vm->user_ctx);
vm->ip += 3;
}
switch (opcode)
{
case 0xa0:
case 0xa1:
vm->ip = addr;
break;
case 0xa2:
case 0xa3:
if (vm->mem_read(vm->ip, false, vm->user_ctx) == 0x9d) {
embedvm_push(vm, vm->sfp | 1);
embedvm_push(vm, vm->ip + 1);
} else {
embedvm_push(vm, vm->sfp);
embedvm_push(vm, vm->ip);
}
vm->sfp = vm->sp;
vm->ip = addr;
break;
case 0xa4:
case 0xa5:
if (embedvm_pop(vm))
vm->ip = addr;
break;
case 0xa6:
case 0xa7:
if (!embedvm_pop(vm))
vm->ip = addr;
break;
}
break;
case 0xae:
embedvm_push(vm, vm->sp);
vm->ip++;
break;
case 0xaf:
embedvm_push(vm, vm->sfp);
vm->ip++;
break;
case 0xb0 ... 0xb0+15:
{
uint8_t argc = embedvm_pop(vm);
int16_t argv[argc];
for (sfa=0; sfa<argc; sfa++)
argv[sfa] = embedvm_pop(vm);
a = vm->call_user(opcode - 0xb0, argc, argv, vm->user_ctx);
embedvm_push(vm, a);
}
vm->ip++;
break;
case 0xc0 ... 0xef:
if ((opcode & 0x07) == 5) {
/* this is a "bury" instruction */
uint8_t depth = (opcode >> 3) & 0x07;
int16_t stack[depth+1];
for (sfa = 0; sfa <= depth; sfa++)
stack[sfa] = embedvm_pop(vm);
embedvm_push(vm, stack[0]);
for (sfa = depth; sfa > 0; sfa--)
embedvm_push(vm, stack[sfa]);
embedvm_push(vm, stack[0]);
vm->ip++;
break;
}
if ((opcode & 0x07) == 6) {
/* this is a "dig" instruction */
uint8_t depth = (opcode >> 3) & 0x07;
int16_t stack[depth+2];
for (sfa = 0; sfa < depth+2; sfa++)
stack[sfa] = embedvm_pop(vm);
for (sfa = depth+1; sfa > 0; sfa--)
embedvm_push(vm, stack[sfa-1]);
embedvm_push(vm, stack[depth+1]);
vm->ip++;
break;
}
sfa = ((opcode >> 3) & 0x07) == 4 || ((opcode >> 3) & 0x07) == 5 ? 1 : 0;
switch (opcode & 0x07)
{
case 0:
addr = vm->mem_read(vm->ip+1, false, vm->user_ctx) & 0x00ff;
vm->ip += 2;
break;
case 1:
addr = vm->mem_read(vm->ip+1, true, vm->user_ctx);
vm->ip += 3;
break;
case 2:
addr = embedvm_pop(vm);
vm->ip++;
break;
case 3:
addr = (embedvm_pop(vm) << sfa) + (vm->mem_read(vm->ip+1, false, vm->user_ctx) & 0x00ff);
vm->ip += 2;
break;
case 4:
addr = (embedvm_pop(vm) << sfa) + vm->mem_read(vm->ip+1, true, vm->user_ctx);
vm->ip += 3;
break;
}
switch ((opcode >> 3) & 0x07)
{
case 0:
embedvm_push(vm, vm->mem_read(addr, false, vm->user_ctx) & 0x00ff);
break;
case 1:
vm->mem_write(addr, embedvm_pop(vm), false, vm->user_ctx);
break;
case 2:
embedvm_push(vm, signext(vm->mem_read(addr, false, vm->user_ctx), 0x00ff));
break;
case 3:
vm->mem_write(addr, embedvm_pop(vm), false, vm->user_ctx);
break;
case 4:
embedvm_push(vm, vm->mem_read(addr, true, vm->user_ctx));
break;
case 5:
vm->mem_write(addr, embedvm_pop(vm), true, vm->user_ctx);
break;
}
break;
case 0xf0 ... 0xf7:
for (sfa = 0; sfa <= (opcode & 0x07); sfa++)
embedvm_push(vm, 0);
vm->ip++;
break;
case 0xf8 ... 0xff:
a = embedvm_pop(vm);
vm->sp += 2 + 2*(opcode & 0x07);
embedvm_push(vm, a);
vm->ip++;
break;
}
}
void embedvm_interrupt(struct embedvm_s *vm, uint16_t addr)
{
embedvm_push(vm, vm->sfp | 1);
embedvm_push(vm, vm->ip);
vm->sfp = vm->sp;
vm->ip = addr;
}
int16_t embedvm_pop(struct embedvm_s *vm)
{
int16_t value = vm->mem_read(vm->sp, true, vm->user_ctx);
vm->sp += 2;
return value;
}
void embedvm_push(struct embedvm_s *vm, int16_t value)
{
vm->sp -= 2;
vm->mem_write(vm->sp, value, true, vm->user_ctx);
}
int16_t embedvm_local_read(struct embedvm_s *vm, int8_t sfa)
{
uint16_t addr = vm->sfp - 2*sfa + (sfa < 0 ? +2 : -2);
return vm->mem_read(addr, true, vm->user_ctx);
}
void embedvm_local_write(struct embedvm_s *vm, int8_t sfa, int16_t value)
{
uint16_t addr = vm->sfp - 2*sfa + (sfa < 0 ? +2 : -2);
vm->mem_write(addr, value, true, vm->user_ctx);
}

53
ui/embedvm.h Normal file
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@ -0,0 +1,53 @@
/*
* EmbedVM - Embedded Virtual Machine for uC Applications
*
* Copyright (C) 2011 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#ifndef EMBEDVM_H
#define EMBEDVM_H
#include <stdint.h>
#include <stdbool.h>
#ifdef __cplusplus
extern "C" {
#endif
struct embedvm_s
{
uint16_t ip, sp, sfp;
void *user_ctx;
int16_t (*mem_read)(uint16_t addr, bool is16bit, void *ctx);
void (*mem_write)(uint16_t addr, int16_t value, bool is16bit, void *ctx);
int16_t (*call_user)(uint8_t funcid, uint8_t argc, int16_t *argv, void *ctx);
};
extern void embedvm_exec(struct embedvm_s *vm);
extern void embedvm_interrupt(struct embedvm_s *vm, uint16_t addr);
int16_t embedvm_pop(struct embedvm_s *vm);
void embedvm_push(struct embedvm_s *vm, int16_t value);
int16_t embedvm_local_read(struct embedvm_s *vm, int8_t sfa);
void embedvm_local_write(struct embedvm_s *vm, int8_t sfa, int16_t value);
#ifdef __cplusplus
}
#endif
#endif

BIN
ui/fonts/DroidSans-Bold.ttf Normal file

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@ -0,0 +1,261 @@
/* -FreeType-Droid_Sans-Bold-R-Normal--11-80-96-96-P-63-ISO10646-1 */
#define FONT_WIDTH_Droid_SansBold_11x14 11
#define FONT_HEIGHT_Droid_SansBold_11x14 14
const uint8_t FONT_DATA_Droid_SansBold_11x14[256][29] = {
{/*w*/3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x00,0x00,0x00,0x0c,0x00,0x0c,0x00,0x0c,0x00,0x0c,0x00,0x0c,0x00,0x00,0x00,0x0c,0x00,0x0c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x00,0x14,0x00,0x14,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/7,0x00,0x00,0x00,0x00,0x00,0x00,0x48,0x00,0x48,0x00,0xfe,0x00,0x68,0x00,0x2c,0x00,0xfe,0x00,0x24,0x00,0x24,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/6,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x3c,0x00,0x0a,0x00,0x0e,0x00,0x1c,0x00,0x38,0x00,0x2a,0x00,0x1e,0x00,0x08,0x00,0x00,0x00,0x00,0x00,},
{/*w*/10,0x00,0x00,0x00,0x00,0x00,0x00,0x8c,0x00,0x52,0x00,0x52,0x00,0x2c,0x00,0xa0,0x01,0x50,0x02,0x50,0x02,0x88,0x01,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/8,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x00,0x24,0x00,0x24,0x00,0x18,0x00,0xde,0x00,0x72,0x00,0x76,0x00,0xdc,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x04,0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x00,0x08,0x00,0x0c,0x00,0x04,0x00,0x04,0x00,0x04,0x00,0x04,0x00,0x0c,0x00,0x08,0x00,0x18,0x00,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x04,0x00,0x0c,0x00,0x08,0x00,0x08,0x00,0x08,0x00,0x08,0x00,0x0c,0x00,0x04,0x00,0x06,0x00,0x00,0x00,},
{/*w*/6,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x2a,0x00,0x3e,0x00,0x14,0x00,0x14,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/6,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x08,0x00,0x3e,0x00,0x08,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x0c,0x00,0x04,0x00,0x00,0x00,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0e,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0c,0x00,0x0c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x10,0x00,0x10,0x00,0x08,0x00,0x08,0x00,0x04,0x00,0x04,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/6,0x00,0x00,0x00,0x00,0x00,0x00,0x1c,0x00,0x36,0x00,0x36,0x00,0x36,0x00,0x36,0x00,0x36,0x00,0x36,0x00,0x1c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/6,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x00,0x1c,0x00,0x1a,0x00,0x18,0x00,0x18,0x00,0x18,0x00,0x18,0x00,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/6,0x00,0x00,0x00,0x00,0x00,0x00,0x1c,0x00,0x36,0x00,0x30,0x00,0x30,0x00,0x18,0x00,0x0c,0x00,0x06,0x00,0x3e,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/6,0x00,0x00,0x00,0x00,0x00,0x00,0x1e,0x00,0x30,0x00,0x30,0x00,0x0c,0x00,0x30,0x00,0x30,0x00,0x32,0x00,0x1e,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
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{/*w*/7,0x00,0x00,0x00,0x00,0x2c,0x00,0x34,0x00,0x00,0x00,0x3c,0x00,0x66,0x00,0x42,0x00,0x42,0x00,0x66,0x00,0x3c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/7,0x00,0x00,0x00,0x00,0x6c,0x00,0x6c,0x00,0x00,0x00,0x3c,0x00,0x66,0x00,0x42,0x00,0x42,0x00,0x66,0x00,0x3c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/6,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x00,0x00,0x00,0x00,0x00,0x7e,0x00,0x00,0x00,0x00,0x00,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/7,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3c,0x00,0x66,0x00,0x52,0x00,0x4a,0x00,0x66,0x00,0x3c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/7,0x00,0x00,0x00,0x00,0x0c,0x00,0x18,0x00,0x00,0x00,0x42,0x00,0x42,0x00,0x42,0x00,0x42,0x00,0x66,0x00,0x5c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/7,0x00,0x00,0x00,0x00,0x30,0x00,0x18,0x00,0x00,0x00,0x42,0x00,0x42,0x00,0x42,0x00,0x42,0x00,0x66,0x00,0x5c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/7,0x00,0x00,0x00,0x00,0x18,0x00,0x24,0x00,0x00,0x00,0x42,0x00,0x42,0x00,0x42,0x00,0x42,0x00,0x66,0x00,0x5c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/7,0x00,0x00,0x00,0x00,0x6c,0x00,0x6c,0x00,0x00,0x00,0x42,0x00,0x42,0x00,0x42,0x00,0x42,0x00,0x66,0x00,0x5c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/6,0x00,0x00,0x00,0x00,0x30,0x00,0x18,0x00,0x00,0x00,0x22,0x00,0x36,0x00,0x14,0x00,0x14,0x00,0x14,0x00,0x08,0x00,0x08,0x00,0x0c,0x00,0x06,0x00,},
{/*w*/7,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x02,0x00,0x3a,0x00,0x66,0x00,0x42,0x00,0x42,0x00,0x66,0x00,0x3a,0x00,0x02,0x00,0x02,0x00,0x02,0x00,},
{/*w*/6,0x00,0x00,0x00,0x00,0x36,0x00,0x36,0x00,0x00,0x00,0x22,0x00,0x36,0x00,0x14,0x00,0x14,0x00,0x14,0x00,0x08,0x00,0x08,0x00,0x0c,0x00,0x06,0x00,},
};

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ui/fonts/DroidSans.h Normal file
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@ -0,0 +1,261 @@
/* -FreeType-Droid Sans-Medium-R-Normal--8-60-96-96-P-44-ISO10646-1 */
#define FONT_WIDTH_Droid SansMedium_13x14 13
#define FONT_HEIGHT_Droid SansMedium_13x14 14
const uint8_t FONT_DATA_Droid SansMedium_13x14[256][29] = {
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x00,0x00,0x10,0x00,0x00,0x00,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc0,0x00,0xc0,0x00,0xf0,0x01,0xf0,0x01,0x60,0x00,0x60,0x00,0x00,0x00,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x70,0x00,0x30,0x00,0x30,0x00,0x60,0x00,0x60,0x00,0x70,0x00,0x20,0x00,0x00,0x00,},
{/*w*/7,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x01,0xb0,0x00,0xb0,0x03,0x70,0x03,0x40,0x03,0x20,0x03,0x00,0x00,0x00,0x00,},
{/*w*/6,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf0,0x00,0x90,0x00,0x60,0x00,0x50,0x02,0x90,0x01,0xf0,0x01,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x20,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x08,0x00,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x70,0x00,0x20,0x00,0x50,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x00,0x40,0x00,0xe0,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x00,0x10,0x00,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x00,0x00,0x00,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x00,0x40,0x00,0x20,0x00,0x20,0x00,0x10,0x00,0x10,0x00,0x00,0x00,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x50,0x00,0x50,0x00,0x50,0x00,0x50,0x00,0x20,0x00,0x00,0x00,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x30,0x00,0x20,0x00,0x20,0x00,0x20,0x00,0x20,0x00,0x00,0x00,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x70,0x00,0x40,0x00,0x40,0x00,0x20,0x00,0x20,0x00,0x70,0x00,0x00,0x00,0x00,0x00,},
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{/*w*/5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xa0,0x00,0x00,0x00,0x60,0x00,0x90,0x00,0x90,0x00,0x60,0x00,0x00,0x00,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0xe0,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x00,0xd0,0x00,0xb0,0x00,0x60,0x00,0x00,0x00,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x40,0x00,0x00,0x00,0x90,0x00,0x90,0x00,0x90,0x00,0xf0,0x00,0x00,0x00,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x40,0x00,0x00,0x00,0x90,0x00,0x90,0x00,0x90,0x00,0xf0,0x00,0x00,0x00,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x00,0xa0,0x00,0x00,0x00,0x90,0x00,0x90,0x00,0x90,0x00,0xf0,0x00,0x00,0x00,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xa0,0x00,0x00,0x00,0x90,0x00,0x90,0x00,0x90,0x00,0xf0,0x00,0x00,0x00,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x00,0x20,0x00,0x00,0x00,0x50,0x00,0x50,0x00,0x50,0x00,0x20,0x00,0x20,0x00,0x10,0x00,},
{/*w*/5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x00,0x10,0x00,0x70,0x00,0x90,0x00,0x90,0x00,0x70,0x00,0x10,0x00,0x10,0x00,},
{/*w*/4,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x50,0x00,0x00,0x00,0x50,0x00,0x50,0x00,0x50,0x00,0x20,0x00,0x20,0x00,0x10,0x00,},
};

BIN
ui/fonts/DroidSans.ttf Normal file

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2927
ui/fonts/DroidSans8x11.bdf Normal file

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261
ui/fonts/DroidSans8x11.h Normal file
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@ -0,0 +1,261 @@
/* -FreeType-Droid Sans-Medium-R-Normal--8-60-96-96-P-44-ISO10646-1 */
#define FONT_WIDTH_Droid_SansMedium_8x11 8
#define FONT_HEIGHT_Droid_SansMedium_8x11 11
const uint8_t FONT_DATA_Droid_SansMedium_8x11[256][12] = {
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x02,0x02,0x02,0x02,0x00,0x02,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x0c,0x0c,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x18,0x18,0x3e,0x3e,0x0c,0x0c,0x00,0x00,},
{/*w*/4,0x00,0x00,0x04,0x0e,0x06,0x06,0x0c,0x0c,0x0e,0x04,0x00,},
{/*w*/7,0x00,0x00,0x00,0x26,0x16,0x76,0x6e,0x68,0x64,0x00,0x00,},
{/*w*/6,0x00,0x00,0x00,0x1e,0x12,0x0c,0x4a,0x32,0x3e,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x04,0x04,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x04,0x02,0x02,0x02,0x02,0x02,0x04,0x00,},
{/*w*/2,0x00,0x00,0x00,0x01,0x02,0x02,0x02,0x02,0x02,0x01,0x00,},
{/*w*/4,0x00,0x00,0x00,0x04,0x0e,0x04,0x0a,0x00,0x00,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x00,0x08,0x08,0x1c,0x08,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x02,0x00,},
{/*w*/3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x08,0x08,0x04,0x04,0x02,0x02,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x04,0x0a,0x0a,0x0a,0x0a,0x04,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x04,0x06,0x04,0x04,0x04,0x04,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x0e,0x08,0x08,0x04,0x04,0x0e,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x0e,0x08,0x04,0x08,0x08,0x0e,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x08,0x0c,0x0c,0x0a,0x1e,0x08,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x0e,0x02,0x0e,0x08,0x08,0x06,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x0c,0x02,0x0e,0x0a,0x0a,0x0c,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x0e,0x08,0x08,0x04,0x04,0x04,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x0e,0x0a,0x0a,0x04,0x0a,0x0e,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x06,0x0a,0x0a,0x0e,0x08,0x06,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x02,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x02,0x02,0x00,},
{/*w*/4,0x00,0x00,0x00,0x00,0x08,0x04,0x06,0x08,0x00,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x00,0x00,0x0e,0x00,0x0e,0x00,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x00,0x02,0x04,0x0c,0x02,0x00,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x0e,0x08,0x08,0x04,0x00,0x04,0x00,0x00,},
{/*w*/7,0x00,0x00,0x00,0x3c,0x42,0x5a,0x5a,0x7a,0x02,0x3c,0x00,},
{/*w*/6,0x00,0x00,0x00,0x08,0x14,0x14,0x1c,0x22,0x22,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x1e,0x12,0x1e,0x12,0x12,0x1e,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x1c,0x02,0x02,0x02,0x02,0x1c,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x0e,0x12,0x12,0x12,0x12,0x0e,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x0e,0x02,0x0e,0x02,0x02,0x0e,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x0e,0x02,0x0e,0x02,0x02,0x02,0x00,0x00,},
{/*w*/6,0x00,0x00,0x00,0x3c,0x02,0x02,0x32,0x22,0x3c,0x00,0x00,},
{/*w*/6,0x00,0x00,0x00,0x22,0x22,0x3e,0x22,0x22,0x22,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x04,0x04,0x04,0x04,0x04,0x04,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x01,},
{/*w*/5,0x00,0x00,0x00,0x12,0x0a,0x06,0x0a,0x0a,0x12,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x02,0x02,0x02,0x02,0x02,0x1e,0x00,0x00,},
{/*w*/8,0x00,0x00,0x00,0x82,0xc6,0xc6,0xaa,0xaa,0x92,0x00,0x00,},
{/*w*/6,0x00,0x00,0x00,0x22,0x26,0x2a,0x2a,0x32,0x22,0x00,0x00,},
{/*w*/6,0x00,0x00,0x00,0x1c,0x22,0x22,0x22,0x22,0x1c,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x1e,0x12,0x12,0x0e,0x02,0x02,0x00,0x00,},
{/*w*/6,0x00,0x00,0x00,0x1c,0x22,0x22,0x22,0x22,0x1c,0x10,0x00,},
{/*w*/5,0x00,0x00,0x00,0x1e,0x12,0x12,0x0e,0x0a,0x12,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x0e,0x02,0x06,0x08,0x08,0x0e,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x0e,0x04,0x04,0x04,0x04,0x04,0x00,0x00,},
{/*w*/6,0x00,0x00,0x00,0x22,0x22,0x22,0x22,0x22,0x1c,0x00,0x00,},
{/*w*/6,0x00,0x00,0x00,0x22,0x22,0x14,0x14,0x14,0x08,0x00,0x00,},
{/*w*/8,0x00,0x00,0x00,0x92,0xaa,0xaa,0xaa,0x64,0x44,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x12,0x0c,0x0c,0x0c,0x0a,0x12,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x11,0x0a,0x0a,0x04,0x04,0x04,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x1e,0x08,0x08,0x04,0x04,0x1e,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x0c,0x04,0x04,0x04,0x04,0x04,0x0c,0x00,},
{/*w*/3,0x00,0x00,0x00,0x02,0x02,0x04,0x04,0x08,0x08,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x03,0x02,0x02,0x02,0x02,0x02,0x03,0x00,},
{/*w*/4,0x00,0x00,0x00,0x08,0x0c,0x12,0x12,0x00,0x00,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0e,},
{/*w*/5,0x00,0x00,0x08,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x00,0x00,0x0e,0x08,0x0e,0x0e,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x02,0x02,0x0e,0x12,0x12,0x0e,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x00,0x00,0x0c,0x02,0x02,0x0c,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x10,0x10,0x1c,0x12,0x12,0x1c,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x00,0x00,0x0e,0x0e,0x02,0x0e,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x06,0x02,0x06,0x02,0x02,0x02,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x00,0x00,0x1e,0x0a,0x0e,0x1c,0x12,0x1e,},
{/*w*/5,0x00,0x00,0x00,0x02,0x02,0x1e,0x12,0x12,0x12,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x02,0x00,0x02,0x02,0x02,0x02,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x02,0x00,0x02,0x02,0x02,0x02,0x02,0x03,},
{/*w*/4,0x00,0x00,0x00,0x02,0x02,0x0a,0x06,0x06,0x0a,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x02,0x02,0x02,0x02,0x02,0x02,0x00,0x00,},
{/*w*/8,0x00,0x00,0x00,0x00,0x00,0xee,0x92,0x92,0x92,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x00,0x00,0x1e,0x12,0x12,0x12,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x00,0x00,0x0c,0x12,0x12,0x0c,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x00,0x00,0x0e,0x12,0x12,0x0e,0x02,0x02,},
{/*w*/5,0x00,0x00,0x00,0x00,0x00,0x1c,0x12,0x12,0x1c,0x10,0x10,},
{/*w*/3,0x00,0x00,0x00,0x00,0x00,0x06,0x02,0x02,0x02,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x00,0x00,0x0e,0x06,0x08,0x0e,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x00,0x02,0x06,0x02,0x02,0x06,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x00,0x00,0x12,0x12,0x12,0x1e,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x00,0x00,0x0a,0x0a,0x0a,0x04,0x00,0x00,},
{/*w*/6,0x00,0x00,0x00,0x00,0x00,0x2a,0x2a,0x16,0x14,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x00,0x00,0x0a,0x04,0x04,0x0a,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x00,0x00,0x0a,0x0a,0x0a,0x04,0x04,0x02,},
{/*w*/4,0x00,0x00,0x00,0x00,0x00,0x0e,0x04,0x04,0x0e,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x04,0x04,0x04,0x02,0x04,0x04,0x04,0x00,},
{/*w*/4,0x00,0x00,0x00,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,},
{/*w*/3,0x00,0x00,0x00,0x04,0x04,0x04,0x08,0x04,0x04,0x04,0x00,},
{/*w*/4,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x0c,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x02,0x02,0x02,0x02,},
{/*w*/4,0x00,0x00,0x00,0x08,0x0c,0x04,0x04,0x0c,0x08,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x0c,0x04,0x04,0x0e,0x04,0x0e,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x00,0x00,0x0e,0x0a,0x0e,0x00,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x11,0x0a,0x06,0x0e,0x0e,0x04,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x04,0x04,0x04,0x00,0x00,0x04,0x04,0x04,},
{/*w*/4,0x00,0x00,0x00,0x0e,0x06,0x0a,0x0e,0x08,0x0e,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x14,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/7,0x00,0x00,0x00,0x3c,0x5a,0x4a,0x5a,0x42,0x3c,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x0e,0x0e,0x0e,0x00,0x00,0x00,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x00,0x00,0x14,0x0a,0x0a,0x14,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x00,0x00,0x00,0x0e,0x08,0x00,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x00,0x00,},
{/*w*/7,0x00,0x00,0x00,0x3c,0x7a,0x5a,0x5a,0x42,0x3c,0x00,0x00,},
{/*w*/4,0x00,0x00,0x1e,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x0e,0x0a,0x0e,0x00,0x00,0x00,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x00,0x08,0x08,0x1c,0x08,0x1c,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x0e,0x08,0x04,0x06,0x00,0x00,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x0e,0x08,0x08,0x0e,0x00,0x00,0x00,0x00,},
{/*w*/5,0x00,0x00,0x10,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x00,0x00,0x12,0x12,0x12,0x1e,0x02,0x02,},
{/*w*/5,0x00,0x00,0x00,0x00,0x1e,0x16,0x16,0x16,0x18,0x18,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x04,},
{/*w*/4,0x00,0x00,0x00,0x06,0x04,0x04,0x04,0x00,0x00,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x0e,0x0a,0x0e,0x00,0x00,0x00,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x00,0x00,0x0a,0x14,0x14,0x0a,0x00,0x00,},
{/*w*/6,0x00,0x00,0x00,0x16,0x14,0x6c,0x5c,0x64,0x44,0x00,0x00,},
{/*w*/6,0x00,0x00,0x00,0x16,0x14,0x7c,0x4c,0x24,0x34,0x00,0x00,},
{/*w*/6,0x00,0x00,0x00,0x2e,0x28,0x78,0x5e,0x68,0x48,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x04,0x02,0x02,0x0e,},
{/*w*/6,0x04,0x08,0x00,0x08,0x14,0x14,0x1c,0x22,0x22,0x00,0x00,},
{/*w*/6,0x10,0x08,0x00,0x08,0x14,0x14,0x1c,0x22,0x22,0x00,0x00,},
{/*w*/6,0x08,0x14,0x00,0x08,0x14,0x14,0x1c,0x22,0x22,0x00,0x00,},
{/*w*/6,0x0c,0x10,0x00,0x08,0x14,0x14,0x1c,0x22,0x22,0x00,0x00,},
{/*w*/6,0x00,0x14,0x00,0x08,0x14,0x14,0x1c,0x22,0x22,0x00,0x00,},
{/*w*/6,0x00,0x00,0x18,0x18,0x14,0x14,0x1c,0x22,0x22,0x00,0x00,},
{/*w*/7,0x00,0x00,0x00,0x78,0x18,0x74,0x14,0x1e,0x72,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x1c,0x02,0x02,0x02,0x02,0x1c,0x10,0x10,},
{/*w*/4,0x04,0x08,0x00,0x0e,0x02,0x0e,0x02,0x02,0x0e,0x00,0x00,},
{/*w*/4,0x08,0x04,0x00,0x0e,0x02,0x0e,0x02,0x02,0x0e,0x00,0x00,},
{/*w*/4,0x04,0x0a,0x00,0x0e,0x02,0x0e,0x02,0x02,0x0e,0x00,0x00,},
{/*w*/4,0x00,0x0a,0x00,0x0e,0x02,0x0e,0x02,0x02,0x0e,0x00,0x00,},
{/*w*/4,0x02,0x04,0x00,0x04,0x04,0x04,0x04,0x04,0x04,0x00,0x00,},
{/*w*/4,0x08,0x04,0x00,0x04,0x04,0x04,0x04,0x04,0x04,0x00,0x00,},
{/*w*/4,0x04,0x0a,0x00,0x04,0x04,0x04,0x04,0x04,0x04,0x00,0x00,},
{/*w*/4,0x00,0x0a,0x00,0x04,0x04,0x04,0x04,0x04,0x04,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x0e,0x12,0x17,0x12,0x12,0x0e,0x00,0x00,},
{/*w*/6,0x0c,0x10,0x00,0x22,0x26,0x2a,0x2a,0x32,0x22,0x00,0x00,},
{/*w*/6,0x04,0x08,0x00,0x1c,0x22,0x22,0x22,0x22,0x1c,0x00,0x00,},
{/*w*/6,0x10,0x08,0x00,0x1c,0x22,0x22,0x22,0x22,0x1c,0x00,0x00,},
{/*w*/6,0x08,0x14,0x00,0x1c,0x22,0x22,0x22,0x22,0x1c,0x00,0x00,},
{/*w*/6,0x0c,0x10,0x00,0x1c,0x22,0x22,0x22,0x22,0x1c,0x00,0x00,},
{/*w*/6,0x00,0x14,0x00,0x1c,0x22,0x22,0x22,0x22,0x1c,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x00,0x00,0x14,0x08,0x14,0x00,0x00,0x00,},
{/*w*/6,0x00,0x00,0x00,0x1c,0x32,0x2a,0x2a,0x26,0x1c,0x00,0x00,},
{/*w*/6,0x04,0x08,0x00,0x22,0x22,0x22,0x22,0x22,0x1c,0x00,0x00,},
{/*w*/6,0x10,0x08,0x00,0x22,0x22,0x22,0x22,0x22,0x1c,0x00,0x00,},
{/*w*/6,0x08,0x14,0x00,0x22,0x22,0x22,0x22,0x22,0x1c,0x00,0x00,},
{/*w*/6,0x00,0x14,0x00,0x22,0x22,0x22,0x22,0x22,0x1c,0x00,0x00,},
{/*w*/4,0x08,0x04,0x00,0x11,0x0a,0x0a,0x04,0x04,0x04,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x02,0x0e,0x12,0x12,0x0e,0x02,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x1e,0x12,0x0a,0x0a,0x12,0x1a,0x00,0x00,},
{/*w*/4,0x00,0x00,0x04,0x08,0x00,0x0e,0x08,0x0e,0x0e,0x00,0x00,},
{/*w*/4,0x00,0x00,0x08,0x04,0x00,0x0e,0x08,0x0e,0x0e,0x00,0x00,},
{/*w*/4,0x00,0x00,0x04,0x0a,0x00,0x0e,0x08,0x0e,0x0e,0x00,0x00,},
{/*w*/4,0x00,0x00,0x06,0x08,0x00,0x0e,0x08,0x0e,0x0e,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x0a,0x00,0x0e,0x08,0x0e,0x0e,0x00,0x00,},
{/*w*/4,0x00,0x00,0x0c,0x0c,0x00,0x0e,0x08,0x0e,0x0e,0x00,0x00,},
{/*w*/7,0x00,0x00,0x00,0x00,0x00,0x6e,0x70,0x1e,0x6e,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x00,0x00,0x0c,0x02,0x02,0x0c,0x08,0x08,},
{/*w*/4,0x00,0x00,0x04,0x08,0x00,0x0e,0x0e,0x02,0x0e,0x00,0x00,},
{/*w*/4,0x00,0x00,0x08,0x04,0x00,0x0e,0x0e,0x02,0x0e,0x00,0x00,},
{/*w*/4,0x00,0x00,0x04,0x0a,0x00,0x0e,0x0e,0x02,0x0e,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x0a,0x00,0x0e,0x0e,0x02,0x0e,0x00,0x00,},
{/*w*/2,0x00,0x00,0x01,0x02,0x00,0x02,0x02,0x02,0x02,0x00,0x00,},
{/*w*/2,0x00,0x00,0x04,0x02,0x00,0x02,0x02,0x02,0x02,0x00,0x00,},
{/*w*/2,0x00,0x00,0x02,0x05,0x00,0x02,0x02,0x02,0x02,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x05,0x00,0x02,0x02,0x02,0x02,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x14,0x0c,0x1c,0x12,0x12,0x0c,0x00,0x00,},
{/*w*/5,0x00,0x00,0x0c,0x10,0x00,0x1e,0x12,0x12,0x12,0x00,0x00,},
{/*w*/5,0x00,0x00,0x04,0x08,0x00,0x0c,0x12,0x12,0x0c,0x00,0x00,},
{/*w*/5,0x00,0x00,0x10,0x08,0x00,0x0c,0x12,0x12,0x0c,0x00,0x00,},
{/*w*/5,0x00,0x00,0x08,0x14,0x00,0x0c,0x12,0x12,0x0c,0x00,0x00,},
{/*w*/5,0x00,0x00,0x0c,0x10,0x00,0x0c,0x12,0x12,0x0c,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x14,0x00,0x0c,0x12,0x12,0x0c,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x00,0x08,0x00,0x1c,0x00,0x08,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x00,0x00,0x0c,0x1a,0x16,0x0c,0x00,0x00,},
{/*w*/5,0x00,0x00,0x04,0x08,0x00,0x12,0x12,0x12,0x1e,0x00,0x00,},
{/*w*/5,0x00,0x00,0x10,0x08,0x00,0x12,0x12,0x12,0x1e,0x00,0x00,},
{/*w*/5,0x00,0x00,0x08,0x14,0x00,0x12,0x12,0x12,0x1e,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x14,0x00,0x12,0x12,0x12,0x1e,0x00,0x00,},
{/*w*/4,0x00,0x00,0x08,0x04,0x00,0x0a,0x0a,0x0a,0x04,0x04,0x02,},
{/*w*/5,0x00,0x00,0x00,0x02,0x02,0x0e,0x12,0x12,0x0e,0x02,0x02,},
{/*w*/4,0x00,0x00,0x00,0x0a,0x00,0x0a,0x0a,0x0a,0x04,0x04,0x02,},
};

3090
ui/fonts/DroidSans8x12.bdf Normal file

File diff suppressed because it is too large Load diff

261
ui/fonts/DroidSans8x12.h Normal file
View file

@ -0,0 +1,261 @@
/* -FreeType-Droid_Sans-Medium-R-Normal--9-70-96-96-P-49-ISO10646-1 */
#define FONT_WIDTH_Droid_SansMedium_8x12 8
#define FONT_HEIGHT_Droid_SansMedium_8x12 12
const uint8_t FONT_DATA_Droid_SansMedium_8x12[256][13] = {
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
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{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x02,0x02,0x02,0x02,0x02,},
{/*w*/5,0x00,0x00,0x00,0x08,0x1c,0x02,0x02,0x02,0x1c,0x08,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x1c,0x04,0x04,0x0e,0x04,0x04,0x1e,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x00,0x00,0x1e,0x12,0x12,0x1e,0x00,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x22,0x14,0x14,0x1c,0x08,0x1c,0x08,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x08,0x08,0x08,0x00,0x00,0x00,0x08,0x08,0x08,},
{/*w*/4,0x00,0x00,0x00,0x0e,0x02,0x0e,0x0a,0x0c,0x08,0x0e,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x14,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/7,0x00,0x00,0x00,0x3c,0x42,0x5a,0x4a,0x5a,0x42,0x3c,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x0e,0x0e,0x0e,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x0a,0x14,0x00,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x00,0x00,0x00,0x1e,0x10,0x00,0x00,0x00,0x00,},
{/*w*/3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x00,},
{/*w*/7,0x00,0x00,0x00,0x3c,0x42,0x7a,0x5a,0x5a,0x42,0x3c,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x3e,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x0e,0x0a,0x0e,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x00,0x08,0x08,0x1e,0x08,0x00,0x1e,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x0e,0x08,0x04,0x0e,0x00,0x00,0x00,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x0e,0x08,0x08,0x0e,0x00,0x00,0x00,0x00,0x00,},
{/*w*/5,0x00,0x00,0x10,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x00,0x00,0x12,0x12,0x12,0x12,0x1e,0x02,0x02,},
{/*w*/6,0x00,0x00,0x00,0x3c,0x2e,0x2e,0x2e,0x28,0x28,0x28,0x28,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x04,0x04,},
{/*w*/4,0x00,0x00,0x00,0x06,0x04,0x04,0x04,0x00,0x00,0x00,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x0e,0x0a,0x0e,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x00,0x00,0x00,0x0a,0x14,0x0a,0x00,0x00,0x00,},
{/*w*/7,0x00,0x00,0x00,0x26,0x14,0x14,0x6c,0x54,0x74,0x42,0x00,0x00,},
{/*w*/7,0x00,0x00,0x00,0x26,0x14,0x14,0x7c,0x44,0x24,0x72,0x00,0x00,},
{/*w*/8,0x00,0x00,0x00,0x4e,0x28,0x28,0xde,0xa8,0xe8,0x84,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x04,0x04,0x02,0x02,0x0e,},
{/*w*/6,0x04,0x08,0x00,0x08,0x14,0x14,0x14,0x1c,0x22,0x22,0x00,0x00,},
{/*w*/6,0x10,0x08,0x00,0x08,0x14,0x14,0x14,0x1c,0x22,0x22,0x00,0x00,},
{/*w*/6,0x08,0x14,0x00,0x08,0x14,0x14,0x14,0x1c,0x22,0x22,0x00,0x00,},
{/*w*/6,0x2c,0x34,0x00,0x08,0x14,0x14,0x14,0x1c,0x22,0x22,0x00,0x00,},
{/*w*/6,0x00,0x14,0x00,0x08,0x14,0x14,0x14,0x1c,0x22,0x22,0x00,0x00,},
{/*w*/6,0x00,0x1c,0x14,0x1c,0x14,0x14,0x14,0x1c,0x22,0x22,0x00,0x00,},
{/*w*/8,0x00,0x00,0x00,0xf8,0x18,0x14,0xf4,0x1c,0x12,0xf2,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x1c,0x02,0x02,0x02,0x02,0x02,0x1c,0x10,0x10,},
{/*w*/5,0x04,0x08,0x00,0x1e,0x02,0x02,0x1e,0x02,0x02,0x1e,0x00,0x00,},
{/*w*/5,0x10,0x08,0x00,0x1e,0x02,0x02,0x1e,0x02,0x02,0x1e,0x00,0x00,},
{/*w*/5,0x08,0x14,0x00,0x1e,0x02,0x02,0x1e,0x02,0x02,0x1e,0x00,0x00,},
{/*w*/5,0x00,0x14,0x00,0x1e,0x02,0x02,0x1e,0x02,0x02,0x1e,0x00,0x00,},
{/*w*/4,0x02,0x04,0x00,0x06,0x04,0x04,0x04,0x04,0x04,0x06,0x00,0x00,},
{/*w*/4,0x08,0x04,0x00,0x06,0x04,0x04,0x04,0x04,0x04,0x06,0x00,0x00,},
{/*w*/4,0x04,0x0a,0x00,0x06,0x04,0x04,0x04,0x04,0x04,0x06,0x00,0x00,},
{/*w*/4,0x00,0x0a,0x00,0x06,0x04,0x04,0x04,0x04,0x04,0x06,0x00,0x00,},
{/*w*/6,0x00,0x00,0x00,0x1e,0x22,0x22,0x27,0x22,0x32,0x1e,0x00,0x00,},
{/*w*/6,0x2c,0x34,0x00,0x22,0x26,0x26,0x2a,0x32,0x32,0x22,0x00,0x00,},
{/*w*/7,0x08,0x10,0x00,0x3c,0x42,0x42,0x42,0x42,0x42,0x3c,0x00,0x00,},
{/*w*/7,0x20,0x10,0x00,0x3c,0x42,0x42,0x42,0x42,0x42,0x3c,0x00,0x00,},
{/*w*/7,0x10,0x28,0x00,0x3c,0x42,0x42,0x42,0x42,0x42,0x3c,0x00,0x00,},
{/*w*/7,0x2c,0x34,0x00,0x3c,0x42,0x42,0x42,0x42,0x42,0x3c,0x00,0x00,},
{/*w*/7,0x00,0x28,0x00,0x3c,0x42,0x42,0x42,0x42,0x42,0x3c,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x00,0x00,0x14,0x08,0x14,0x00,0x00,0x00,0x00,},
{/*w*/7,0x00,0x00,0x00,0x3c,0x62,0x52,0x52,0x4a,0x46,0x3c,0x00,0x00,},
{/*w*/6,0x04,0x08,0x00,0x22,0x22,0x22,0x22,0x22,0x22,0x1c,0x00,0x00,},
{/*w*/6,0x10,0x08,0x00,0x22,0x22,0x22,0x22,0x22,0x22,0x1c,0x00,0x00,},
{/*w*/6,0x08,0x14,0x00,0x22,0x22,0x22,0x22,0x22,0x22,0x1c,0x00,0x00,},
{/*w*/6,0x00,0x14,0x00,0x22,0x22,0x22,0x22,0x22,0x22,0x1c,0x00,0x00,},
{/*w*/6,0x10,0x08,0x00,0x22,0x12,0x14,0x08,0x08,0x08,0x08,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x02,0x0e,0x12,0x12,0x0e,0x02,0x02,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x1e,0x12,0x0a,0x0a,0x12,0x12,0x1a,0x00,0x00,},
{/*w*/5,0x00,0x00,0x04,0x08,0x00,0x1e,0x10,0x1e,0x12,0x1e,0x00,0x00,},
{/*w*/5,0x00,0x00,0x10,0x08,0x00,0x1e,0x10,0x1e,0x12,0x1e,0x00,0x00,},
{/*w*/5,0x00,0x00,0x08,0x14,0x00,0x1e,0x10,0x1e,0x12,0x1e,0x00,0x00,},
{/*w*/5,0x00,0x00,0x16,0x1a,0x00,0x1e,0x10,0x1e,0x12,0x1e,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x14,0x00,0x1e,0x10,0x1e,0x12,0x1e,0x00,0x00,},
{/*w*/5,0x00,0x1c,0x14,0x1c,0x00,0x1e,0x10,0x1e,0x12,0x1e,0x00,0x00,},
{/*w*/8,0x00,0x00,0x00,0x00,0x00,0x6e,0x90,0xfe,0x12,0xee,0x00,0x00,},
{/*w*/4,0x00,0x00,0x00,0x00,0x00,0x0c,0x02,0x02,0x02,0x0c,0x08,0x08,},
{/*w*/5,0x00,0x00,0x04,0x08,0x00,0x0c,0x12,0x1e,0x02,0x1c,0x00,0x00,},
{/*w*/5,0x00,0x00,0x10,0x08,0x00,0x0c,0x12,0x1e,0x02,0x1c,0x00,0x00,},
{/*w*/5,0x00,0x00,0x08,0x14,0x00,0x0c,0x12,0x1e,0x02,0x1c,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x14,0x00,0x0c,0x12,0x1e,0x02,0x1c,0x00,0x00,},
{/*w*/2,0x00,0x00,0x01,0x02,0x00,0x02,0x02,0x02,0x02,0x02,0x00,0x00,},
{/*w*/2,0x00,0x00,0x04,0x02,0x00,0x02,0x02,0x02,0x02,0x02,0x00,0x00,},
{/*w*/2,0x00,0x00,0x02,0x05,0x00,0x02,0x02,0x02,0x02,0x02,0x00,0x00,},
{/*w*/2,0x00,0x00,0x00,0x05,0x00,0x02,0x02,0x02,0x02,0x02,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x14,0x0c,0x10,0x1c,0x12,0x12,0x0c,0x00,0x00,},
{/*w*/5,0x00,0x00,0x16,0x1a,0x00,0x1e,0x12,0x12,0x12,0x12,0x00,0x00,},
{/*w*/5,0x00,0x00,0x04,0x08,0x00,0x0c,0x12,0x12,0x12,0x0c,0x00,0x00,},
{/*w*/5,0x00,0x00,0x10,0x08,0x00,0x0c,0x12,0x12,0x12,0x0c,0x00,0x00,},
{/*w*/5,0x00,0x00,0x08,0x14,0x00,0x0c,0x12,0x12,0x12,0x0c,0x00,0x00,},
{/*w*/5,0x00,0x00,0x16,0x1a,0x00,0x0c,0x12,0x12,0x12,0x0c,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x14,0x00,0x0c,0x12,0x12,0x12,0x0c,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x00,0x08,0x00,0x3e,0x00,0x08,0x00,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x00,0x00,0x1c,0x1a,0x1a,0x16,0x0e,0x00,0x00,},
{/*w*/5,0x00,0x00,0x04,0x08,0x00,0x12,0x12,0x12,0x12,0x1e,0x00,0x00,},
{/*w*/5,0x00,0x00,0x10,0x08,0x00,0x12,0x12,0x12,0x12,0x1e,0x00,0x00,},
{/*w*/5,0x00,0x00,0x08,0x14,0x00,0x12,0x12,0x12,0x12,0x1e,0x00,0x00,},
{/*w*/5,0x00,0x00,0x00,0x14,0x00,0x12,0x12,0x12,0x12,0x1e,0x00,0x00,},
{/*w*/5,0x00,0x00,0x10,0x08,0x00,0x12,0x12,0x0c,0x0c,0x0c,0x04,0x06,},
{/*w*/5,0x00,0x00,0x00,0x02,0x02,0x0e,0x12,0x12,0x12,0x0e,0x02,0x02,},
{/*w*/5,0x00,0x00,0x00,0x14,0x00,0x12,0x12,0x0c,0x0c,0x0c,0x04,0x06,},
};

File diff suppressed because it is too large Load diff

View file

@ -0,0 +1,261 @@
/* -FreeType-Droid_Sans-Bold-R-Normal--9-70-96-96-P-49-ISO10646-1 */
#define FONT_WIDTH_Droid_SansBold_8x12 8
#define FONT_HEIGHT_Droid_SansBold_8x12 12
const uint8_t FONT_DATA_Droid_SansBold_8x12[256][13] = {
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
{/*w*/0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,},
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};

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