120 lines
3.7 KiB
C
120 lines
3.7 KiB
C
#ifndef _MW_ACC_H
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#define _MW_ACC_H
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#define KIONIX_DEVICE_ADDRESS ( 0x0F )
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/* KIONIX accelerometer register addresses */
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#define KIONIX_XOUT_HPF_L ( 0x00 )
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#define KIONIX_XOUT_HPF_H ( 0x01 )
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#define KIONIX_YOUT_HPF_L ( 0x02 )
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#define KIONIX_YOUT_HPF_H ( 0x03 )
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#define KIONIX_ZOUT_HPF_L ( 0x04 )
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#define KIONIX_ZOUT_HPF_H ( 0x05 )
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#define KIONIX_XOUT_L ( 0x06 )
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#define KIONIX_XOUT_H ( 0x07 )
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#define KIONIX_YOUT_L ( 0x08 )
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#define KIONIX_YOUT_H ( 0x09 )
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#define KIONIX_ZOUT_L ( 0x0A )
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#define KIONIX_ZOUT_H ( 0x0B )
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#define KIONIX_DCST_RESP ( 0x0C )
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#define KIONIX_WHO_AM_I ( 0x0F )
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#define KIONIX_TILT_POS_CUR ( 0x10 )
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#define KIONIX_TILT_POS_PRE ( 0x11 )
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#define KIONIX_INT_SRC_REG1 ( 0x15 )
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#define KIONIX_INT_SRC_REG2 ( 0x16 )
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#define KIONIX_STATUS_REG ( 0x18 )
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#define KIONIX_INT_REL ( 0x1A )
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#define KIONIX_CTRL_REG1 ( 0x1B )
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#define KIONIX_CTRL_REG2 ( 0x1C )
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#define KIONIX_CTRL_REG3 ( 0x1D )
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#define KIONIX_INT_CTRL_REG1 ( 0x1E )
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#define KIONIX_INT_CTRL_REG2 ( 0x1F )
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#define KIONIX_INT_CTRL_REG3 ( 0x20 )
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#define KIONIX_DATA_CTRL_REG ( 0x21 )
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#define KIONIX_TILT_TIMER ( 0x28 )
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#define KIONIX_WUF_TIMER ( 0x29 )
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#define KIONIX_TDT_TIMER ( 0x2B )
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#define KIONIX_TDT_H_THRESH ( 0x2C )
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#define KIONIX_TDT_L_THRESH ( 0x2D )
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#define KIONIX_TDT_TAP_TIMER ( 0x2E )
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#define KIONIX_TDT_TOTAL_TIMER ( 0x2F )
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#define KIONIX_TDT_LATENCY_TIMER ( 0x30 )
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#define KIONIX_TDT_WINDOW_TIMER ( 0x31 )
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#define KIONIX_SELF_TEST ( 0x3A )
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#define KIONIX_WUF_THRESH ( 0x5A )
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#define KIONIX_TILT_ANGLE ( 0x5C )
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#define KIONIX_HYST_SET ( 0x5F )
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/* CTRL_REG1 */
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#define PC1_STANDBY_MODE ( 0 << 7 )
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#define PC1_OPERATING_MODE ( 1 << 7 )
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#define RESOLUTION_8BIT ( 0 << 6 )
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#define RESOLUTION_12BIT ( 1 << 6 )
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#define DRDYE_DATA_AVAILABLE ( 1 << 5 )
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#define WUF_ENABLE ( 1 << 1 )
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#define TAP_ENABLE_TDTE ( 1 << 2 )
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#define TILT_ENABLE_TPE ( 1 << 0 )
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/* CTRL_REG2 */
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#define TILT_LEM (1 << 5 )
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#define TILT_RIM (1 << 4 )
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#define TILT_DOM (1 << 3 )
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#define TILT_UPM (1 << 2 )
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#define TILT_FDM (1 << 1 )
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#define TILT_FUM (1 << 0 )
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/* CTRL_REG3 */
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#define SRST ( 1 << 7 )
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#define TILT_ODR_1_6HZ ( 0 << 5 )
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#define TILT_ODR_6_3HZ ( 1 << 5 )
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#define TILT_ODR_12_5HZ ( 2 << 5 )
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#define TILT_ODR_50HZ ( 3 << 5 )
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#define DCST ( 1 << 4 )
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#define TAP_ODR_50HZ ( 0 << 2 )
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#define TAP_ODR_100HZ ( 1 << 2 )
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#define TAP_ODR_200HZ ( 2 << 2 )
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#define TAP_ODR_400HZ ( 3 << 2 )
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#define WUF_ODR_25HZ ( 0 << 0 )
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#define WUF_ODR_50HZ ( 1 << 0 )
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#define WUF_ODR_100HZ ( 2 << 0 )
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#define WUF_ODR_200HZ ( 3 << 0 )
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/* INT_CTRL_REG1 */
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#define IEN ( 1 << 5 )
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#define IEA ( 1 << 4 )
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#define IEL ( 1 << 3 )
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#define IEU ( 1 << 2 )
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/* INT_CTRL_REG2 */
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#define XBW ( 1 << 7 )
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#define YBW ( 1 << 6 )
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#define ZBW ( 1 << 5 )
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/* INT_CTRL_REG3 */
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#define TLEM (1 << 5)
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#define TRIM (1 << 4)
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#define TDOM (1 << 3)
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#define TUPM (1 << 2)
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#define TFDM (1 << 1)
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#define TFUM (1 << 0)
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/* INT_SRC_REG2 */
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#define INT_TPS 0x01
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#define INT_WUFS 0x02
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#define INT_TAP_SINGLE 0x04
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#define INT_TAP_DOUBLE 0x08
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#define INT_DRDY 0x10
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void mw_acc_init_i2c(void);
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void mw_acc_disable_i2c(void);
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void mw_acc_i2c_read(const uint8_t RegisterAddress, uint8_t *pData, const uint8_t Length);
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void mw_acc_i2c_write(uint8_t RegisterAddress, uint8_t *pData, uint8_t Length);
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void mw_acc_init(void);
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void mw_acc_enable(void);
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void mw_acc_disable(void);
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void mw_acc_read(int16_t *x, int16_t *y, int16_t *z);
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void mw_acc_handle_irq(void);
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#endif
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