462 lines
15 KiB
C
462 lines
15 KiB
C
#ifndef AX110XX_H
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#define AX110XX_H
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/* Byte Registers */
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__sfr __at (0x80) P0; // Port 0
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__sfr __at (0x81) SP; // Stack Pointer
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__sfr __at (0x82) DPL0; // Data Pointer 0 Low Byte
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__sfr __at (0x83) DPH0; // Data Pointer 0 High Byte
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__sfr __at (0x82) DPL; // Data Pointer 0 Low Byte
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__sfr __at (0x83) DPH; // Data Pointer 0 High Byte
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__sfr __at (0x84) DPL1; // Data Pointer 1 Low Byte
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__sfr __at (0x85) DPH1; // Data Pointer 1 High Byte
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__sfr __at (0x86) DPS; // Data Pointers Select Register
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__sfr __at (0x87) PCON; // Power Configuration Register
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__sfr __at (0x88) TCON; // Timer 0,1 Configuration Register
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__sfr __at (0x89) TMOD; // Timer 0,1 Control Mode Register
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__sfr __at (0x8A) TL0; // Timer 0 Low Byte Counter
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__sfr __at (0x8B) TL1; // Timer 1 Low Byte Counter
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__sfr __at (0x8C) TH0; // Timer 0 High Byte Counter
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__sfr __at (0x8D) TH1; // Timer 1 High Byte Counter
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__sfr __at (0x8E) CKCON; // Clock Control Register
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__sfr __at (0x8F) CSREPR; // Software Reset and External Program RAM Select Register
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__sfr __at (0x90) P1; // Port 1
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__sfr __at (0x91) EIF; // Extended Interrupt Flag Register
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__sfr __at (0x92) WTST; // Program Wait States Register
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__sfr __at (0x93) DPX0; // Data Pointer Extended Register 0
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__sfr __at (0x93) DPX; // Data Pointer Extended Register 0
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__sfr __at (0x94) SDSTSR; // Software Timer and Software DMA complete interrupt status
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__sfr __at (0x95) DPX1; // Data Pointer Extended Register 1
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__sfr __at (0x96) I2CCIR; // I2C Command Index Register
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__sfr __at (0x97) I2CDR; // I2C Data Register
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__sfr __at (0x98) SCON0; // UART 0 Configuration Register
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__sfr __at (0x99) SBUF0; // UART 0 Buffer Register
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__sfr __at (0x9A) DBAR; // DMA Bus Arbitration Register
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__sfr __at (0x9B) DCIR; // DMA Command Index Register
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__sfr __at (0x9C) DDR; // DMA Data Register
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__sfr __at (0x9D) ACON; // Address Control Register
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__sfr __at (0x9E) PISSR1; // Peripheral Interrupt Status Summary Register 1
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__sfr __at (0x9F) PISSR2; // Peripheral Interrupt Status Summary Register 2
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__sfr __at (0xA0) P2; // Port 2
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/* Local Bus Master Mode */
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__sfr __at (0xA1) LMSR; // Local Bus Mode Setup Register
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__sfr __at (0xA2) LCR; // Local Bus Command Register
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__sfr __at (0xA3) LSR; // Local Bus Status Register
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__sfr __at (0xA4) LDALR; // Local Bus Device Address Low Register
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__sfr __at (0xA5) LDAHR; // Local Bus Device Address High Register
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__sfr __at (0xA6) LDCSR; // Local Bus Device Chip Select Register
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/* Local Bus Slave Mode */
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__sfr __at (0xA1) LSAIER; // Local Bus Slave mode Action and Interrupt Enable Register
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__sfr __at (0xA2) LSCR; // Local Bus Slave mode Command Register
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__sfr __at (0xA3) LSSR; // Local Bus Slave mode Status Register
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__sfr __at (0xA4) XMWLR; // External Master Write-read Low Register
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__sfr __at (0xA5) XMWHR; // External Master Write-read High Register
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__sfr __at (0xA6) XMRLR; // External Master Read-only Low Register
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__sfr __at (0xA7) XMRHR; // External Master Read-only High Register
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__sfr __at (0xA8) IE; // Interrupt Enable register
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__sfr __at (0xA9) LDLR; // Local Bus Data Low Register
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__sfr __at (0xAA) LDHR; // Local Bus Data High Register
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__sfr __at (0xAB) DMALR; // Local Bus DMA Address Low Register
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__sfr __at (0xAC) DMAMR; // Local Bus DMA Address Medium Register
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__sfr __at (0xAD) DMAHR; // Local Bus DMA Address High Register
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__sfr __at (0xAE) TCIR; // TOE Command Index Register
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__sfr __at (0xAF) TDR; // TOE Data Register
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__sfr __at (0xB0) P3; // Port 3
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__sfr __at (0xB1) CCAPL0; // PCA Module 0 Compare/Capture Low Byte Register
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__sfr __at (0xB2) CCAPL1; // PCA Module 1 Compare/Capture Low Byte Register
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__sfr __at (0xB3) CCAPL2; // PCA Module 2 Compare/Capture Low Byte Register
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__sfr __at (0xB4) CCAPL3; // PCA Module 3 Compare/Capture Low Byte Register
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__sfr __at (0xB5) CCAPL4; // PCA Module 4 Compare/Capture Low Byte Register
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__sfr __at (0xB6) MCIR; // MAC Command Index Register
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__sfr __at (0xB7) MDR; // MAC Data Register
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__sfr __at (0xB8) IP; // Interrupt Priority Register
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__sfr __at (0xB9) CCAPH0; // PCA Module 0 Compare/Capture High Byte Register
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__sfr __at (0xBA) CCAPH1; // PCA Module 1 Compare/Capture High Byte Register
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__sfr __at (0xBB) CCAPH2; // PCA Module 2 Compare/Capture High Byte Register
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__sfr __at (0xBC) CCAPH3; // PCA Module 3 Compare/Capture High Byte Register
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__sfr __at (0xBD) CCAPH4; // PCA Module 4 Compare/Capture High Byte Register
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__sfr __at (0xBE) EPCR; // Ethernet PHY Command Index Register
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__sfr __at (0xBF) EPDR; // Ethernet PHY Data Register
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__sfr __at (0xC0) SCON1; // UART 1 Configuration Register
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__sfr __at (0xC1) SBUF1; // UART 1 Buffer Register
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__sfr __at (0xC2) CMOD; // PCA Timer/Counter Mode Register
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__sfr __at (0xC3) CCON; // PCA Timer/Counter Control Register
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__sfr __at (0xC4) CL; // PCA Timer/Counter Low
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__sfr __at (0xC5) CH; // PCA Timer/Counter High
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__sfr __at (0xC8) T2CON; // Timer 2 Configuration Register
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__sfr __at (0xC9) T2IF; // Timer 2 Interrupt Flags
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__sfr __at (0xCA) RLDL; // Timer 2 Reload Low Byte
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__sfr __at (0xCB) RLDH; // Timer 2 Reload High Byte
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__sfr __at (0xCC) TL2; // Timer 2 Low Byte Counter
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__sfr __at (0xCD) TH2; // Timer 2 High Byte Counter
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__sfr __at (0xCE) SPICIR; // SPI Command Index Register
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__sfr __at (0xCF) SPIDR; // SPI Data Register
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__sfr __at (0xD0) PSW; // Program Status Word
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__sfr __at (0xD1) CCAPM0; // PCA Compare/Capture Module Mode Register 0
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__sfr __at (0xD2) CCAPM1; // PCA Compare/Capture Module Mode Register 1
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__sfr __at (0xD3) CCAPM2; // PCA Compare/Capture Module Mode Register 2
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__sfr __at (0xD4) CCAPM3; // PCA Compare/Capture Module Mode Register 3
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__sfr __at (0xD5) CCAPM4; // PCA Compare/Capture Module Mode Register 4
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__sfr __at (0xD6) OWCIR; // OneWire Command Index Register
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__sfr __at (0xD7) OWDR; // OneWire Data Register
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__sfr __at (0xD8) WDCON; // Watchdog Configuration
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__sfr __at (0xDE) CANCIR; // CAN Bus Command Index Register
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__sfr __at (0xDF) CANDR; // CAN Bus Data Register
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__sfr __at (0xE0) ACC; // Accumulator
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/* UART2 registers */
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__sfr __at (0xE1) UR2_DLL;// High Speed UART2 Divisor Latch Low Register
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__sfr __at (0xE1) UR2_THR;// High Speed UART2 Transmit Holding Register for Writing
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__sfr __at (0xE1) UR2_RBR;// High Speed UART2 Receive Buffer Register for Reading
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__sfr __at (0xE2) UR2_DLH;// High Speed UART2 Divisor Latch High Register
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__sfr __at (0xE2) UR2_IER;// High Speed UART2 Interrupt Enable Register
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__sfr __at (0xE3) UR2_FCR;// High Speed UART2 FIFO Control Register for Writing
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__sfr __at (0xE3) UR2_IIR;// High Speed UART2 Interrupt Identification Register for Reading
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__sfr __at (0xE4) UR2_LCR;// High Speed UART2 Line Control Register
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__sfr __at (0xE5) UR2_MCR;// High Speed UART2 Modem Control Register
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__sfr __at (0xE6) UR2_LSR;// High Speed UART2 Line Status Register
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__sfr __at (0xE7) UR2_MSR;// High Speed UART2 Modem Status Register
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__sfr __at (0xE8) EIE; // External Interrupt Enable
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__sfr __at (0xE9) STATUS; // Status Register
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__sfr __at (0xEA) MXAX; // MOVX @Ri Extended Register
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__sfr __at (0xEB) TA; // Timed Access Protection
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__sfr __at (0xF0) B; // B Working Register
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__sfr __at (0xF8) EIP; // Extended Interrupt Priority Register
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__sfr __at (0xF9) MD0; // MDU Data 0
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__sfr __at (0xFA) MD1; // MDU Data 1
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__sfr __at (0xFB) MD2; // MDU Data 2
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__sfr __at (0xFC) MD3; // MDU Data 3
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__sfr __at (0xFD) MD4; // MDU Data 4
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__sfr __at (0xFE) MD5; // MDU Data 5
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__sfr __at (0xFF) ARCON ;// MDU Control Register
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/* Bit Registers */
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/* P0 (0x80) Bit Registers */
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__sbit __at (0x80) P0_0;
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__sbit __at (0x81) P0_1;
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__sbit __at (0x82) P0_2;
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__sbit __at (0x83) P0_3;
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__sbit __at (0x84) P0_4;
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__sbit __at (0x85) P0_5;
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__sbit __at (0x86) P0_6;
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__sbit __at (0x87) P0_7;
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/* DPS (0x86) Bit Values */
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#define SEL_ 0x01
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#define TSL_ 0x20
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#define ID0_ 0x40
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#define ID1_ 0x80
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/* PCON (0x87) Bit Values */
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#define PMM_ 0x01
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#define STOP_ 0x02
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#define SWB_ 0x04
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#define PWE_ 0x10
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#define SMOD1_ 0x40
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#define SMOD2_ 0x80
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/* TCON (0x88) Bit Registers */
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__sbit __at (0x88) IT0;
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__sbit __at (0x89) IE0;
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__sbit __at (0x8A) IT1;
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__sbit __at (0x8B) IE1;
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__sbit __at (0x8C) TR0;
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__sbit __at (0x8D) TF0;
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__sbit __at (0x8E) TR1;
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__sbit __at (0x8F) TF1;
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/* TMOD (0x89) Bit Values */
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#define T0_M0_ 0x01
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#define T0_M1_ 0x02
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#define T0_CT_ 0x04
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#define T0_GATE_ 0x08
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#define T1_M0_ 0x10
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#define T1_M1_ 0x20
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#define T1_CT_ 0x40
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#define T1_GATE_ 0x80
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#define T1_MASK_ 0xF0
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#define T0_MASK_ 0x0F
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/* CKCON (0x8E) Bit Values */
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#define MD0_ 0x01
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#define MD1_ 0x02
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#define MD2_ 0x04
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#define T0M_ 0x08
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#define T1M_ 0x10
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#define T2M_ 0x20
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#define WD0_ 0x40
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#define WD1_ 0x80
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/* CSREPR (0x8F) Bit Values */
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#define SW_RST 0x01
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#define SW_RBT 0x02
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#define FARM 0x04
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#define FAES 0x08
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#define PMS 0x10
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#define SCS_100M 0xC0
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#define SCS_75M 0x80
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#define SCS_50M 0x40
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#define SCS_25M 0x00
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/* P1 (0x90) Bit Registers */
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__sbit __at (0x90) P1_0;
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__sbit __at (0x91) P1_1;
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__sbit __at (0x92) P1_2;
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__sbit __at (0x93) P1_3;
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__sbit __at (0x94) P1_4;
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__sbit __at (0x95) P1_5;
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__sbit __at (0x96) P1_6;
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__sbit __at (0x97) P1_7;
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/* EIF (0x91) Bit Values */
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#define INT2F 0x01
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#define INT3F 0x02
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#define INT4F 0x04
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#define INT5F 0x08
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#define INT6F 0x10
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/* SCON0 (0x98) Bit Registers */
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__sbit __at (0x98) RI0;
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__sbit __at (0x99) TI0;
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__sbit __at (0x9A) RB08;
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__sbit __at (0x9B) TB08;
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__sbit __at (0x9C) REN0;
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__sbit __at (0x9D) SM02;
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__sbit __at (0x9E) SM01;
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__sbit __at (0x9F) SM00;
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/* DBAR (0x9A) Bit Values */
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#define BUS_REQ 0x01
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#define BUS_GRANT 0x80
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/* ACON (0x9D) Bit Values */
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#define FLAT_MODE 0x02
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#define LARGE_MODE 0x00
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/* PISSR1 (0x9E) Bit Values */
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#define LB_INT_STU 0x01
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#define LB_EXT_INT_STU 0x02
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#define ETH_INT_STU 0x04
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#define TOE_INT_STU 0x08
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#define OW_INT_STU 0x10
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#define SPI_INT_STU 0x20
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#define I2C_INT_STU 0x40
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#define CAN_INT_STU 0x80
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/* PISSR2 (0x9F) Bit Values */
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#define UART2_INT_STU 0x01
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/* P2 (0xA0) Bit Registers */
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__sbit __at (0xA0) P2_0;
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__sbit __at (0xA1) P2_1;
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__sbit __at (0xA2) P2_2;
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__sbit __at (0xA3) P2_3;
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__sbit __at (0xA4) P2_4;
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__sbit __at (0xA5) P2_5;
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__sbit __at (0xA6) P2_6;
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__sbit __at (0xA7) P2_7;
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/* IE (0xA8) Bit Registers */
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__sbit __at (0xA8) EX0; /* 1=Enable External interrupt 0 */
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__sbit __at (0xA9) ET0; /* 1=Enable Timer 0 interrupt */
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__sbit __at (0xAA) EX1; /* 1=Enable External interrupt 1 */
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__sbit __at (0xAB) ET1; /* 1=Enable Timer 1 interrupt */
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__sbit __at (0xAC) ES0; /* 1=Enable Serial port 0 interrupt */
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__sbit __at (0xAD) ET2; /* 1=Enable Timer 2 interrupt */
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__sbit __at (0xAE) ES1; /* 1=Enable Serial port 1 interrupt */
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__sbit __at (0xAF) EA; /* 0=Disable all interrupts */
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/* P3 (0xB0) Bit Registers (Mnemonics & Ports) */
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__sbit __at (0xB0) P3_0;
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__sbit __at (0xB1) P3_1;
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__sbit __at (0xB2) P3_2;
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__sbit __at (0xB3) P3_3;
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__sbit __at (0xB4) P3_4;
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__sbit __at (0xB5) P3_5;
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__sbit __at (0xB6) P3_6;
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__sbit __at (0xB7) P3_7;
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__sbit __at (0xB0) RXD; /* Serial data input */
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__sbit __at (0xB1) TXD; /* Serial data output */
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__sbit __at (0xB2) INT0; /* External interrupt 0 */
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__sbit __at (0xB3) INT1; /* External interrupt 1 */
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__sbit __at (0xB4) T0; /* Timer 0 external input */
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__sbit __at (0xB5) T1; /* Timer 1 external input */
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__sbit __at (0xB6) WR; /* External data memory write strobe */
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__sbit __at (0xB7) RD; /* External data memory read strobe */
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/* IP (0xB8) Bit Registers */
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__sbit __at (0xB8) PX0;
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__sbit __at (0xB9) PT0;
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__sbit __at (0xBA) PX1;
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__sbit __at (0xBB) PT1;
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__sbit __at (0xBC) PS0;
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__sbit __at (0xBD) PT2;
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__sbit __at (0xBE) PS1;
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/* SCON1 (0xC0) Bit Registers */
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__sbit __at (0xC0) RI1;
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__sbit __at (0xC1) TI1;
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__sbit __at (0xC2) RB18;
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__sbit __at (0xC3) TB18;
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__sbit __at (0xC4) REN1;
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__sbit __at (0xC5) SM12;
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__sbit __at (0xC6) SM11;
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__sbit __at (0xC7) SM10;
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/* CMOM (0xC2) Bit Values */
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#define PCA_ECF 0x01
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#define PCA_T0_OF 0x08
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#define PCA_EXT_CLK 0x0E
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#define PCA_GATE_OFF 0x80
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/* CCON (0xC3) Bit Values */
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#define PCA_CCF0 0x01
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#define PCA_CCF1 0x02
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#define PCA_CCF2 0x04
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#define PCA_CCF3 0x08
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#define PCA_CCF4 0x10
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#define PCA_CR 0x40
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#define PCA_CF 0x80
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/* T2CON (0xC8) Bit Registers */
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__sbit __at (0xC8) CPRL2;
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__sbit __at (0xC9) CT2;
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__sbit __at (0xCA) TR2;
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__sbit __at (0xCB) EXEN2;
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__sbit __at (0xCC) TCLK;
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__sbit __at (0xCD) RCLK;
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__sbit __at (0xCE) EXF2;
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__sbit __at (0xCF) TF2;
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/* PSW (0xD0) Bit Registers */
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__sbit __at (0xD0) P;
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__sbit __at (0xD1) F1;
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__sbit __at (0xD2) OV;
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__sbit __at (0xD3) RS0;
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__sbit __at (0xD4) RS1;
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__sbit __at (0xD5) F0;
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__sbit __at (0xD6) AC;
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__sbit __at (0xD7) CY;
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/* CCAPM0-4 (0xD1-0xD5) Bit Values */
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#define ECCFs 0x01
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#define PWMs 0x02
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#define TOGs 0x04
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#define MATs 0x08
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#define CAPNs 0x10
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#define CAPPs 0x20
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#define ECOMs 0x40
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#define CEXs 0x80
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/* PSW (0xD8) Bit Registers */
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__sbit __at (0xD8) RWT;
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__sbit __at (0xD9) EWT;
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__sbit __at (0xDA) WTRF;
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__sbit __at (0xDB) WDIF;
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/* Interrupt Vectors: Address = (N * 8) + 3 */
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#define IE0_VECTOR 0 /* 0x03 External Interrupt 0 */
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#define TF0_VECTOR 1 /* 0x0B Timer 0 */
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#define IE1_VECTOR 2 /* 0x13 External Interrupt 1 */
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#define TF1_VECTOR 3 /* 0x1B Timer 1 */
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#define SIO0_VECTOR 4 /* 0x23 Serial port */
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#define TF2_VECTOR 5 /* 0x2B Timer 2 */
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#define SIO1_VECTOR 6 /* 0x33 Serial port */
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#define DMA_VECTOR 7 /* 0x3B Internal DMA Transfer */
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#define PCA_VECTOR 8 /* 0x43 Internal Programmable Counter Array */
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#define PIR_VECTOR 9 /* 0x4B Internal Peripherial IRQ */
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#define SDMA_VECTOR 10 /* 0x53 Internal Software DMA */
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#define WU_VECTOR 11 /* 0x5B Wake-Up */
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#define WDT_VECTOR 12 /* 0x63 Internal Watchdog */
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/* UR2_IER (0xE2) Bit Values */
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#define UR2_RDI_ENB 0x01
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#define UR2_THRI_ENB 0x02
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#define UR2_RLSI_ENB 0x04
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#define UR2_MSI_ENB 0x08
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/* UR2_IIR (0xE3) Bit Values */
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#define UR2_NONE_INTR 0x01
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#define UR2_RLS_INTR 0x06
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#define UR2_RD_TRIG_INTR 0x04
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#define UR2_RD_TI_INTR 0x0C
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#define UR2_THRE_INTR 0x02
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#define UR2_MS_INTR 0x00
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/* UR2_FCR (0xE3) Bit Values */
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#define UR2_FIFO_MODE 0x01
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#define UR2_RXFIFO_RST 0x02
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#define UR2_TXFIFO_RST 0x04
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#define UR2_TRIG_01 0x00
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#define UR2_TRIG_04 0x40
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#define UR2_TRIG_08 0x80
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#define UR2_TRIG_14 0xC0
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/* UR2_LCR (0xE4) Bit Values */
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#define UR2_CHAR_5 0x00
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#define UR2_CHAR_6 0x01
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#define UR2_CHAR_7 0x02
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#define UR2_CHAR_8 0x03
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#define UR2_STOP_10 0x00
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#define UR2_STOP_15 0x04
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#define UR2_PARITY_ENB 0x08
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#define UR2_EVEN_PARITY 0x10
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#define UR2_STICK_PARITY 0x20
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#define UR2_BREAK_ENB 0x40
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#define UR2_DLAB_ENB 0x80
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/* UR2_MCR (0xE5) Bit Values */
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#define UR2_DTR 0x01
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#define UR2_RTS 0x02
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#define UR2_OUT1 0x04
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#define UR2_OUT2 0x08
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#define UR2_LOOPBACK 0x10
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#define UR2_RS485_RECEIVE 0x40
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#define UR2_RS485_DRIVE 0x80
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/* UR2_LSR (0xE6) Bit Values */
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#define UR2_DR 0x01
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#define UR2_OE 0x02
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#define UR2_PE 0x04
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#define UR2_FE 0x08
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#define UR2_BI 0x10
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#define UR2_THRE 0x20
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#define UR2_TEMT 0x40
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#define UR2_FRAME_ERR 0x80
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/* UR2_MSR (0xE7) Bit Values */
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#define UR2_DCTS 0x01
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#define UR2_DDSR 0x02
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#define UR2_TERI 0x04
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#define UR2_DDCD 0x08
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#define UR2_CTS 0x10
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#define UR2_DSR 0x20
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#define UR2_RI 0x40
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#define UR2_DCD 0x80
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/* EIE (0xE8) Bit Registers */
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__sbit __at (0xE8) EINT2;
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__sbit __at (0xE9) EINT3;
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__sbit __at (0xEA) EINT4;
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__sbit __at (0xEB) EINT5;
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__sbit __at (0xEC) EINT6;
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__sbit __at (0xED) EWDI;
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/* EIP (0xF8) Bit Registers */
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__sbit __at (0xF8) PINT2;
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__sbit __at (0xF9) PINT3;
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__sbit __at (0xFA) PINT4;
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__sbit __at (0xFB) PINT5;
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__sbit __at (0xFC) PINT6;
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__sbit __at (0xFD) PWDI;
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#endif
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