199 lines
6.7 KiB
ArmAsm
199 lines
6.7 KiB
ArmAsm
/*
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crt.s - startup code
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Copyright (C) 2007 Ch. Klippel <ck@mamalala.net>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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.global main
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.global _etext
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.global _data
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.global _edata
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.global __bss_start
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.global __bss_end__
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.global _stack
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/* Stack Sizes */
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.set UND_STACK_SIZE, 0x00000004 /* stack for "undefined instruction" interrupts is 4 bytes */
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.set ABT_STACK_SIZE, 0x00000004 /* stack for "abort" interrupts is 4 bytes */
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.set FIQ_STACK_SIZE, 0x00000004 /* stack for "FIQ" interrupts is 4 bytes */
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.set IRQ_STACK_SIZE, 0X00000100 /* stack for "IRQ" normal interrupts is 4 bytes */
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.set SVC_STACK_SIZE, 0x00000004 /* stack for "SVC" supervisor mode is 4 bytes */
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/* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */
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.set MODE_USR, 0x10 /* Normal User Mode */
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.set MODE_FIQ, 0x11 /* FIQ Processing Fast Interrupts Mode */
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.set MODE_IRQ, 0x12 /* IRQ Processing Standard Interrupts Mode */
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.set MODE_SVC, 0x13 /* Supervisor Processing Software Interrupts Mode */
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.set MODE_ABT, 0x17 /* Abort Processing memory Faults Mode */
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.set MODE_UND, 0x1B /* Undefined Processing Undefined Instructions Mode */
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.set MODE_SYS, 0x1F /* System Running Priviledged Operating System Tasks Mode */
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.set I_BIT, 0x80 /* when I bit is set, IRQ is disabled (program status registers) */
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.set F_BIT, 0x40 /* when F bit is set, FIQ is disabled (program status registers) */
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.text
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.arm
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.global Reset_Handler
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.global _startup
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.global _endstartup
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.global ramvectors
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.func ramvectors
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ramvectors:
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ldr PC, Ram_Reset_Addr
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ldr PC, Ram_Undef_Addr
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ldr PC, Ram_SWI_Addr
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ldr PC, Ram_PAbt_Addr
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ldr PC, Ram_DAbt_Addr
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nop /* Reserved Vector (holds Philips ISP checksum) */
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ldr PC, [PC,#-0xFF0] /* Route IRQ to VIC */
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ldr PC, Ram_FIQ_Addr
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Ram_Reset_Addr: .word Reset_Handler /* defined in this module below */
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Ram_Undef_Addr: .word UNDEF_Routine /* defined in main.c */
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Ram_SWI_Addr: .word SWI_Routine /* defined in main.c */
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Ram_PAbt_Addr: .word UNDEF_Routine /* defined in main.c */
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Ram_DAbt_Addr: .word UNDEF_Routine /* defined in main.c */
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Ram_IRQ_Addr: .word IRQ_Routine /* defined in main.c */
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Ram_FIQ_Addr: .word FIQ_Routine /* defined in main.c */
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.word 0 /* rounds vectors to 64 bytes total */
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.endfunc
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.section .text
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.func _startup
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_startup:
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# Exception Vectors
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_vectors:
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ldr PC, Reset_Addr
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Reset_Addr: .word Reset_Handler
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# Reset Handler
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Reset_Handler:
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/* Setup a stack for each mode - note that this only sets up a usable stack
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for User mode. Also each mode is setup with interrupts initially disabled. */
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ldr r0, =_stack_end
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msr CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode */
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mov sp, r0
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sub r0, r0, #UND_STACK_SIZE
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msr CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */
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mov sp, r0
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sub r0, r0, #ABT_STACK_SIZE
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msr CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */
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mov sp, r0
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sub r0, r0, #FIQ_STACK_SIZE
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msr CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */
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mov sp, r0
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sub r0, r0, #IRQ_STACK_SIZE
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msr CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */
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mov sp, r0
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sub r0, r0, #SVC_STACK_SIZE
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msr CPSR_c, #MODE_SYS|I_BIT|F_BIT /* User Mode */
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mov sp, r0
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/* Setup Pins and Memory */
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ldr r0,=BCFG0
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ldr r1, =0x10000420
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str r1,[r0]
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str r1,[r0,#0x08]
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ldr r0, =BCFG1
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ldr r1, =0xc42
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str r1, [r0]
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ldr r0, =PINSEL0
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ldr r1, =0x00008005
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str r1, [r0]
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ldr r0, =PINSEL1
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ldr r1, =0x20000000
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str r1, [r0]
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ldr r0, =PINSEL2
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ldr r1, =0x0de049d4
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str r1, [r0]
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ldr r0, = IO2SET
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ldr r1, =0x1FC0000
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str r1, [r0]
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str r1, [r0,#0x04]
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ldr r0, = IO0DIR
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ldr r1, =0x002018D0
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str r1, [r0]
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/* Setup PLL */
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ldr r0, =0xe01fc000
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ldr r2, =0xaa
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ldr r3, =0x55
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ldr r1, =0x03
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str r1, [r0,#0x80]
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ldr r1, =0x0
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str r1, [r0,#0x100]
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ldr r1, =0x42
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str r1,[r0,#0x84]
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str r2, [r0,#0x8c]
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str r3, [r0,#0x8c]
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_endstartup:
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/* Copy .fastcode & .data section (Copy from ROM to RAM) */
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ldr R0, =ramvectors /*_etext*/
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ldr r3, entry_mask /* this and the next instruction are an workaround */
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and r0, r0, r3 /* for some ugly bug in winarm to force msb to 0x80 */
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ldr R1, =0x40000000 /*_data*/
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ldr R2, =_startup
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1:
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cmp r1,r2
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ldmltia r0!,{r3}
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stmltia r1!,{r3}
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blt 1b
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/* Clear .bss section (Zero init) */
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mov R0, #0
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ldr R1, =_bss_start
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ldr R2, =_bss_end
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2:
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cmp R1, R2
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strlo R0, [R1], #4
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blo 2b
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ldr r0, =MEMMAP
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ldr r1, =0x02 /* irq vectors in ram */
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str r1, [r0]
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mov r0,#0
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mov r1,r0
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mov r2,r0
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mov fp,r0
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mov r7,r0
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ldr r10,=main
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mov lr,pc
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bx r10
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.endfunc
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entry_mask: .word 0x4FFFFFFF /* defined in this module below */
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.end
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