diff --git a/boop/Makefile b/boop/Makefile
index 8a4eaf4..1f49ca1 100644
--- a/boop/Makefile
+++ b/boop/Makefile
@@ -55,7 +55,7 @@ ifeq ($(MAKECMDGOALS),debug)
 	COMPILE += -D DEBUGMODE
 	OPTFLAGS = -O0
 else
-	OPTFLAGS = -Os
+	OPTFLAGS = -Og 
 endif
 
 ifeq ($(MAKECMDGOALS),release)
diff --git a/boop/boop_rom.bin b/boop/boop_rom.bin
index d799393..33ec32b 100644
Binary files a/boop/boop_rom.bin and b/boop/boop_rom.bin differ
diff --git a/boop/cc1100/cc1100.c b/boop/cc1100/cc1100.c
index 4874ca2..02b9c80 100644
--- a/boop/cc1100/cc1100.c
+++ b/boop/cc1100/cc1100.c
@@ -26,58 +26,74 @@
 #include "cc1100.h"
 #include "irq.h"
 
-//setting 6_WOR
-const unsigned char conf[0x2F] = {   
-	0x29,	// IOCFG2
-	0x2E,	// IOCFG1
-	0x06,	// IOCFG0
-	0x47,	// FIFOTHR
-	0xD3,	// SYNC1
-	0x91,	// SYNC0
-	0x3E,	// PKTLEN
-	0x1A,	// PKTCTRL1
-	0x45,	// PKTCTRL0
-	0x01,	// ADDR
-	0x01,	// CHANNR
-	0x06,	// FSCTRL1
-	0x00,	// FSCTRL0
-	0x10,	// FREQ2		#
-	0x0B,	// FREQ1		#
-	0xDA,	// FREQ0		# -> 433,249969 MHz
-	0x8A,	// MDMCFG4
-	0x75,	// MDMCFG3
-	0x13,	// MDMCFG2
-	0x22,	// MDMCFG1
-	0xC1,	// MDMCFG0	CHANSPC_M
-	0x35,	// DEVIATN
-	0x04,	// MCSM2
-	0x0C,	// MCSM1 0c
-	0x38,	// MCSM0
-	0x16,	// FOCCFG
-	0x6C,	// BSCFG
-	0x43,	// AGCCTRL2
-	0x40,	// AGCCTRL1
-	0x91,	// AGCCTRL0
-	0x46,	// WOREVT1
-	0x50,	// WOREVT0
-	0x78,	// WORCTRL
-	0x56,	// FREND1
-	0x10,	// FREND0
-	0xA9,	// FSCAL3
-	0x0A,	// FSCAL2
-	0x00,	// FSCAL1
-	0x11,	// FSCAL0
-	0x41,	// RCCTRL1
-	0x00,	// RCCTRL0
-	0x57,	// FSTEST
-	0x7F,	// PTEST
-	0x3F,	// AGCTEST
-	0x98,	// TEST2
-	0x31,	// TEST1
-	0x0B	// TEST0
+// Deviation = 21.423340
+// Base frequency = 433.254913
+// Carrier frequency = 433.254913
+// Channel number = 0
+// Carrier frequency = 433.254913
+// Modulated = true
+// Modulation format = GFSK
+// Manchester enable = false
+// Sync word qualifier mode = 30/32 sync word bits detected
+// Preamble count = 4
+// Channel spacing = 184.982300
+// Carrier frequency = 433.254913
+// Data rate = 37.4908
+// RX filter BW = 210.937500
+// Data format = Normal mode
+// CRC enable = true
+// Whitening = false
+// Device address = 1
+// Address config = Address check and 0 (0x00) broadcast
+// CRC autoflush = true
+// PA ramping = false
+// TX power = 0
+// Rf settings for CC1101
+const unsigned char conf[] = {
+    0x29,  // IOCFG2        GDO2 Output Pin Configuration
+    0x2E,  // IOCFG1        GDO1 Output Pin Configuration
+    0x06,  // IOCFG0        GDO0 Output Pin Configuration
+    0x47,  // FIFOTHR       RX FIFO and TX FIFO Thresholds
+    0xD3,  // SYNC1         Sync Word, High Byte
+    0x91,  // SYNC0         Sync Word, Low Byte
+    0x3E,  // PKTLEN        Packet Length
+    0x1A,  // PKTCTRL1      Packet Automation Control
+    0x05,  // PKTCTRL0      Packet Automation Control
+    0x01,  // ADDR          Device Address
+    0x00,  // CHANNR        Channel Number
+    0x06,  // FSCTRL1       Frequency Synthesizer Control
+    0x00,  // FSCTRL0       Frequency Synthesizer Control
+    0x10,  // FREQ2         Frequency Control Word, High Byte
+    0x0B,  // FREQ1         Frequency Control Word, Middle Byte
+    0xE6,  // FREQ0         Frequency Control Word, Low Byte
+    0x8A,  // MDMCFG4       Modem Configuration
+    0x6C,  // MDMCFG3       Modem Configuration
+    0x13,  // MDMCFG2       Modem Configuration
+    0x22,  // MDMCFG1       Modem Configuration
+    0xC1,  // MDMCFG0       Modem Configuration
+    0x35,  // DEVIATN       Modem Deviation Setting
+    0x04,  // MCSM2         Main Radio Control State Machine Configuration
+    0x0C,  // MCSM1         Main Radio Control State Machine Configuration
+    0x38,  // MCSM0         Main Radio Control State Machine Configuration
+    0x16,  // FOCCFG        Frequency Offset Compensation Configuration
+    0x6C,  // BSCFG         Bit Synchronization Configuration
+    0x43,  // AGCCTRL2      AGC Control
+    0x40,  // AGCCTRL1      AGC Control
+    0x91,  // AGCCTRL0      AGC Control
+    0x46,  // WOREVT1       High Byte Event0 Timeout
+    0x50,  // WOREVT0       Low Byte Event0 Timeout
+    0x78,  // WORCTRL       Wake On Radio Control
+    0x56,  // FREND1        Front End RX Configuration
+    0x10,  // FREND0        Front End TX Configuration
+    0xE9,  // FSCAL3        Frequency Synthesizer Calibration
+    0x2A,  // FSCAL2        Frequency Synthesizer Calibration
+    0x00,  // FSCAL1        Frequency Synthesizer Calibration
+    0x1F,  // FSCAL0        Frequency Synthesizer Calibration
+    0x41,  // RCCTRL1       RC Oscillator Configuration
+    0x00,  // RCCTRL0       RC Oscillator Configuration
 };
 
-const unsigned char confasync[0x2F] = {   
+const unsigned char confasync[] = {
 	0x0D,	// IOCFG2
 	0x0D,	// IOCFG1
 	0x2E,	// IOCFG0
@@ -120,12 +136,6 @@ const unsigned char confasync[0x2F] = {
 	0x1F,	// FSCAL0
 	0x41,	// RCCTRL1
 	0x00,	// RCCTRL0
-	0x59,	// FSTEST
-	0x7F,	// PTEST
-	0x3F,	// AGCTEST
-	0x81,	// TEST2
-	0x35,	// TEST1
-	0x09	// TEST0
 };
 
 void cc1100_init(void) {
@@ -164,7 +174,7 @@ void cc1100_init(void) {
 	while (SSPSR & (1<<4));
 	xx = SSPDR;
 		
-	cc1100_write((0x00 | BURST ),(unsigned char*)conf,0x2f);
+	cc1100_write((0x00 | BURST ),(unsigned char*)conf,sizeof(conf));
 	cc1100_write1(PATABLE,0xC0);
 	cc1100_strobe(SIDLE);
 	cc1100_strobe(SPWD);
diff --git a/boop/cc1100/cc1100.h b/boop/cc1100/cc1100.h
index 3e0b3c7..f4cc27a 100644
--- a/boop/cc1100/cc1100.h
+++ b/boop/cc1100/cc1100.h
@@ -118,8 +118,8 @@
 #define MARCSTATE_IDLE	0x01
 #define MARCSTATE_RX	0x0d
 
-const unsigned char conf[0x2F] __attribute__((aligned(0x4)));
-const unsigned char confasync[0x2F] __attribute__((aligned(0x4)));
+extern const unsigned char conf[]; //__attribute__((aligned(0x4)));
+extern const unsigned char confasync[];// __attribute__((aligned(0x4)));
 
 void cc1100_init(void);
 unsigned char cc1100_write(unsigned char addr, unsigned char* data, unsigned char length);
diff --git a/boop/cc1100/rf.c b/boop/cc1100/rf.c
index 62ce2e2..cc93c81 100644
--- a/boop/cc1100/rf.c
+++ b/boop/cc1100/rf.c
@@ -485,14 +485,14 @@ void RFasyncmode(unsigned char on) {
 		RF_changestate(RFidle);
 		while(RF.state != RFidle);
 		stopRFIRQ();
-		cc1100_write((0x00 | BURST ),(unsigned char*)confasync,0x2f);
+		cc1100_write((0x00 | BURST ),(unsigned char*)confasync,sizeof((unsigned char*)confasync));
 		cc1100_write1(PATABLE,0xf0);
 		PINSEL1 &= 0xfffffffc;			// GDO0 as GPIO
 		FIODIR0 |= GDO0;				// output
 	}
 	else {
 		PINSEL1 |= 1;					// GDO0 as EINT0
-		cc1100_write((0x00 | BURST ),(unsigned char*)conf,0x2f);
+		cc1100_write((0x00 | BURST ),(unsigned char*)conf,sizeof((unsigned char*)conf));
 		cc1100_write1(PATABLE,0xC0);
 		cc1100_strobe(SIDLE);
 		load_RF_setting();
diff --git a/boop/gui/testmenu.c b/boop/gui/testmenu.c
index 333fed4..ce4d331 100644
--- a/boop/gui/testmenu.c
+++ b/boop/gui/testmenu.c
@@ -862,6 +862,35 @@ void test_RF(void) {
 			cur_ep->bufferlen = 3;
 			cur_ep->flags |= EPenabled | EPoutput | EPnewdata | EPonce | EPsendwor;
 			
+			RF_changestate(RFtx);
+		} else if(KEY_1)
+		{
+			struct RFendpoint_* cur_ep;
+
+			cur_ep = openEP(0,0, packet_test);
+			if(cur_ep) {
+				cur_ep->dest = destAddr;
+				cur_ep->data[0] = 'X';
+				cur_ep->data[1] = '1';
+				cur_ep->data[2] = 0x00;
+				cur_ep->bufferlen = 3;
+				cur_ep->flags |= EPenabled | EPoutput | EPnewdata | EPonce;
+
+				RF_changestate(RFtx);
+			}
+		}
+		else if(KEY_2)
+		{
+			struct RFendpoint_* cur_ep;
+
+			cur_ep = openEP(0,0, packet_test);
+			cur_ep->dest = destAddr;
+			cur_ep->data[0] = 'X';
+			cur_ep->data[1] = '2';
+			cur_ep->data[2] = 0x00;
+			cur_ep->bufferlen = 3;
+			cur_ep->flags |= EPenabled | EPoutput | EPnewdata | EPonce ;
+
 			RF_changestate(RFtx);
 		}
 	}
diff --git a/boop/infrared/ir_rf.c b/boop/infrared/ir_rf.c
index b1dcbe3..8032b17 100644
--- a/boop/infrared/ir_rf.c
+++ b/boop/infrared/ir_rf.c
@@ -42,7 +42,7 @@ extern volatile unsigned long keyMap[42];
 #define IRRF_WAIT	0x01
 
 #define IRRF_BITTIME	 40
-#define IRRF_WAITTIME	125
+#define IRRF_WAITTIME	100
 
 void __attribute__ ((section(".text.fastcode"))) IRRF_Encode (void)
 {
@@ -63,6 +63,7 @@ void __attribute__ ((section(".text.fastcode"))) IRRF_Encode (void)
 			}
 			break;
 	}
+	T1MR0 = 15*1000;
 }
 
 void IRRF_Init(unsigned char map)
@@ -100,9 +101,10 @@ void IRRF_Repeat(void)
 			struct RFendpoint_* cur_ep;
 			cur_ep = (struct RFendpoint_*)ir.general.trail;
 			if((cur_ep) && !(cur_ep->flags & EPnewdata)) {
-				cur_ep->dest = (ir.actcmd & 0xff00) >> 8;
-				cur_ep->data[0] = (ir.actcmd & 0x00ff);
-				cur_ep->bufferlen = 1;
+				cur_ep->dest = 0;
+				cur_ep->data[1] = (ir.actcmd & 0x00ff);
+				cur_ep->data[0] = (ir.actcmd & 0xff00) >> 8;
+				cur_ep->bufferlen = 2;
 				cur_ep->flags |= EPenabled | EPoutput | EPnewdata;
 				
 				RF_changestate(RFtx);